Issued Patents All Time
Showing 176–200 of 205 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6271132 | Self-aligned source and drain extensions fabricated in a damascene contact and gate process | Matthew S. Buynoski, Ming-Ren Lin | 2001-08-07 |
| 6255219 | Method for fabricating high-performance submicron MOSFET with lateral asymmetric channel | Wei Long | 2001-07-03 |
| 6255169 | Process for fabricating a high-endurance non-volatile memory device | Xiao-Yu Li, Sunil Mehta | 2001-07-03 |
| 6248675 | Fabrication of field effect transistors having dual gates with gate dielectrics of high dielectric constant using lowered temperatures | Ming-Ren Lin | 2001-06-19 |
| 6239452 | Self-aligned silicide gate technology for advanced deep submicron MOS device | Shekhar Pramanick, Ming-Ren Lin | 2001-05-29 |
| 6218245 | Method for fabricating a high-density and high-reliability EEPROM device | Xiao-Yu Li | 2001-04-17 |
| 6214683 | Process for fabricating a semiconductor device component using lateral metal oxidation | Scott A. Bell, Chih-Yuh Yang | 2001-04-10 |
| 6211044 | Process for fabricating a semiconductor device component using a selective silicidation reaction | Scott A. Bell, Chih-Yuh Yang | 2001-04-03 |
| 6200863 | Process for fabricating a semiconductor device having assymetric source-drain extension regions | Dong-Hyuk Ju | 2001-03-13 |
| 6190952 | Multiple semiconductor-on-insulator threshold voltage circuit | Bin Yu | 2001-02-20 |
| 6187657 | Dual material gate MOSFET technique | Joong S. Jeon | 2001-02-13 |
| 6180469 | Low resistance salicide technology with reduced silicon consumption | Shekhar Pramanick, Ming-Ren Lin | 2001-01-30 |
| 6168999 | Method for fabricating high-performance submicron mosfet with lateral asymmetric channel and a lightly doped drain | Wei Long | 2001-01-02 |
| 6169302 | Determination of parasitic capacitance between the gate and drain/source local interconnect of a field effect transistor | Wei Long, Yowjuang W. Liu | 2001-01-02 |
| 6165902 | Low resistance metal contact technology | Shekhar Pramanick, Ming-Ren Lin | 2000-12-26 |
| 6159782 | Fabrication of field effect transistors having dual gates with gate dielectrics of high dielectric constant | Ming-Ren Lin | 2000-12-12 |
| 6153534 | Method for fabricating a dual material gate of a short channel field effect transistor | Wei Long, Yowjuang W. Liu | 2000-11-28 |
| 6133129 | Method for fabricating a metal structure with reduced length that is beyond photolithography limitations | Scott A. Bell, Chih-Yuh Yang | 2000-10-17 |
| 6121155 | Integrated circuit fabrication critical dimension control using self-limiting resist etch | Chih-Yuh Yang, Scott A. Bell | 2000-09-19 |
| 6093594 | CMOS optimization method utilizing sacrificial sidewall spacer | Geoffrey Choh-Fei Yeap, Ming-Ren Lin | 2000-07-25 |
| 6087696 | Stacked tunneling dielectric technology for improving data retention of EEPROM cell | Xiao-Yu Li, Sunil Mehta | 2000-07-11 |
| 6087231 | Fabrication of dual gates of field transistors with prevention of reaction between the gate electrode and the gate dielectric with a high dielectric constant | Ming-Ren Lin | 2000-07-11 |
| 6060377 | Method for fabricating a polysilicon structure with reduced length that is beyond photolithography limitations | Scott A. Bell, Chih-Yuh Yang | 2000-05-09 |
| 6047243 | Method for quantifying ultra-thin dielectric reliability: time dependent dielectric wear-out | David Bang | 2000-04-04 |
| 6015752 | Elevated salicide technology | Shekhar Pramanick | 2000-01-18 |