Issued Patents All Time
Showing 201–205 of 205 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5994191 | Elevated source/drain salicide CMOS technology | Shekhar Pramanick | 1999-11-30 |
| 5960322 | Suppression of boron segregation for shallow source and drain junctions in semiconductors | Geoffrey Choh-Fei Yeap, Srinath Krishnan, Ming-Ren Lin | 1999-09-28 |
| 5937315 | Self-aligned silicide gate technology for advanced submicron MOS devices | Shekhar Pramanick, Ming-Ren Lin | 1999-08-10 |
| 5937319 | Method of making a metal oxide semiconductor (MOS) transistor polysilicon gate with a size beyond photolithography limitation by using polysilicidation and selective etching | Subash Gupta, Ming-Ren Lin | 1999-08-10 |
| 5866473 | Method of manufacturing a polysilicon gate having a dimension below the photolithography limitation | Ming-Ren Lin | 1999-02-02 |