Issued Patents All Time
Showing 76–100 of 205 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6867080 | Polysilicon tilting to prevent geometry effects during laser thermal annealing | Eric N. Paton, Robert B. Ogle, Cyrus E. Tabery, Bin Yu | 2005-03-15 |
| 6858503 | Depletion to avoid cross contamination | Minh Van Ngo, Ming-Ren Lin, Paul R. Besser, Eric N. Paton, Jung-Suk Goo | 2005-02-22 |
| 6855982 | Self aligned double gate transistor having a strained channel region and process therefor | James Pan, Ming-Ren Lin | 2005-02-15 |
| 6852600 | Strained silicon MOSFET having silicon source/drain regions and method for its fabrication | Haihong Wang | 2005-02-08 |
| 6849527 | Strained silicon MOSFET having improved carrier mobility, strained silicon CMOS device, and methods of their formation | — | 2005-02-01 |
| 6825115 | Post silicide laser thermal annealing to avoid dopant deactivation | Robert B. Ogle, Eric N. Paton, Cyrus E. Tabery, Bin Yu | 2004-11-30 |
| 6812106 | Reduced dopant deactivation of source/drain extensions using laser thermal annealing | Robert B. Ogle, Eric N. Paton, Cyrus E. Tabery, Bin Yu | 2004-11-02 |
| 6811448 | Pre-cleaning for silicidation in an SMOS process | Eric N. Paton, Paul R. Besser | 2004-11-02 |
| 6809016 | Diffusion stop implants to suppress as punch-through in SiGe | — | 2004-10-26 |
| 6800910 | FinFET device incorporating strained silicon in the channel region | Ming-Ren Lin, Jung-Suk Goo, Haihong Wang | 2004-10-05 |
| 6797614 | Nickel alloy for SMOS process silicidation | Eric N. Paton, Paul R. Besser, Minh Van Ngo | 2004-09-28 |
| 6797602 | Method of manufacturing a semiconductor device with supersaturated source/drain extensions and metal silicide contacts | George Jonathan Kluth | 2004-09-28 |
| 6790750 | Semiconductor-on-insulator body-source contact and method | Wei Long, Yowjuang W. Liu | 2004-09-14 |
| 6787423 | Strained-silicon semiconductor device | — | 2004-09-07 |
| 6787864 | Mosfets incorporating nickel germanosilicided gate and methods for their formation | Eric N. Paton, Paul R. Besser, Ming-Ren Lin, Minh Van Ngo, Haihong Wang | 2004-09-07 |
| 6784506 | Silicide process using high K-dielectrics | Paul R. Besser, Matthew S. Buynoski, John Foster, Paul L. King, Eric N. Paton | 2004-08-31 |
| 6780789 | Laser thermal oxidation to form ultra-thin gate oxide | Bin Yu, Robert B. Ogle, Eric N. Paton, Cyrus E. Tabery | 2004-08-24 |
| 6764912 | Passivation of nitride spacer | John Foster, Eric N. Paton, Matthew S. Buynoski, Paul R. Besser, Paul L. King | 2004-07-20 |
| 6764908 | Narrow width CMOS devices fabricated on strained lattice semiconductor substrates with maximized NMOS and PMOS drive currents | Daniel Kadosh, Derick J. Wristers, Bin Yu | 2004-07-20 |
| 6759308 | Silicon on insulator field effect transistor with heterojunction gate | Matthew S. Buynoski | 2004-07-06 |
| 6756276 | Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication | Jung-Suk Goo, Haihong Wang | 2004-06-29 |
| 6747333 | Method and apparatus for STI using passivation material for trench bottom liner | Philip A. Fisher | 2004-06-08 |
| 6746944 | Low nisi/si interface contact resistance with preamorphizing and laser thermal annealing | Robert B. Ogle, Eric N. Paton, Cyrus E. Tabery, Bin Yu | 2004-06-08 |
| 6743689 | Method of fabrication SOI devices with accurately defined monocrystalline source/drain extensions | Eric N. Paton, Robert B. Ogle, Cyrus E. Tabery, Bin Yu | 2004-06-01 |
| 6737337 | Method of preventing dopant depletion in surface semiconductor layer of semiconductor-on-insulator (SOI) device | Simon S. Chan | 2004-05-18 |