Issued Patents All Time
Showing 26–50 of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6947438 | PCI and MII compatible home phoneline networking alliance (HPNA) interface device | Chin-Wei Liang | 2005-09-20 |
| 6906959 | Method and system for erasing a nitride memory device | Mark Randolph, Yi He, Wei Zheng, Edward Franklin Runnion, Zhizheng Liu | 2005-06-14 |
| 6894925 | Flash memory cell programming method and system | Sheunghee Park, Sameer Haddad, Richard Fastow, Ming Sang Kwan, Zhigang Wang | 2005-05-17 |
| 6885590 | Memory device having A P+ gate and thin bottom oxide and method of erasing same | Wei Zheng, Tazrien Kamal | 2005-04-26 |
| 6853645 | PCI and MII compatible home phoneline networking alliance (HPNA) interface device | Chin-Wei Liang | 2005-02-08 |
| 6808996 | Method for protecting gate edges from charge gain/loss in semiconductor device | Tuan Pham, Mark T. Ramsbey, Sameer Haddad, Angela T. Hui, Yu Sun | 2004-10-26 |
| 6806155 | Method and system for scaling nonvolatile memory cells | Kelwin Ko | 2004-10-19 |
| 6787840 | Nitridated tunnel oxide barriers for flash memory technology circuitry | Tuan Pham, Mark T. Ramsbey, Yu Sun | 2004-09-07 |
| 6764929 | Method and system for providing a contact hole in a semiconductor device | Angela T. Hui, Mark S. Chang | 2004-07-20 |
| 6754105 | Trench side wall charge trapping dielectric flash memory device | Wei Zheng, Hidehiko Shiraiwa | 2004-06-22 |
| 6750157 | Nonvolatile memory cell with a nitridated oxide layer | Richard Fastow, Narbeh Derhacobian | 2004-06-15 |
| 6744668 | Flash memory array with dual function control lines and asymmetrical source and drain junctions | Michael A. Van Buskirk | 2004-06-01 |
| 6730564 | Salicided gate for virtual ground arrays | Mark T. Ramsbey, Yu Sun, Hidehiko Shiraiwa | 2004-05-04 |
| 6701406 | PCI and MII compatible home phoneline networking alliance (HPNA) interface device | Chin-Wei Liang, Matthew James Fischer | 2004-03-02 |
| 6664191 | Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space | Unsoon Kim, Yider Wu, Yu Sun, Michael K. Templeton, Angela T. Hui | 2003-12-16 |
| 6653189 | Source side boron implant and drain side MDD implant for deep sub 0.18 micron flash memory | Sameer Haddad, Yue-Song He, Timothy Thurgate, Mark Randolph, Ngaching Wong | 2003-11-25 |
| 6645801 | Salicided gate for virtual ground arrays | Mark T. Ramsbey, Yu Sun | 2003-11-11 |
| 6605511 | Method of forming nitridated tunnel oxide barriers for flash memory technology circuitry and STI and LOCOS isolation | Tuan Pham, Mark T. Ramsbey, Yu Sun | 2003-08-12 |
| 6566194 | Salicided gate for virtual ground arrays | Mark T. Ramsbey, Yu Sun | 2003-05-20 |
| 6549466 | Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure | Narbeh Derhacobian, Michael A. Van Buskirk, Daniel Sobek | 2003-04-15 |
| 6524914 | Source side boron implanting and diffusing device architecture for deep sub 0.18 micron flash memory | Yue-Song He, Sameer Haddad, Timothy Thurgate | 2003-02-25 |
| 6510085 | Method of channel hot electron programming for short channel NOR flash arrays | Richard Fastow, Sheunghee Park, Zhigang Wang, Sameer Haddad | 2003-01-21 |
| 6509604 | Nitridation barriers for nitridated tunnel oxide for circuitry for flash technology and for LOCOS/STI isolation | Tuan Pham, Mark T. Ramsbey, Yu Sun | 2003-01-21 |
| 6509232 | Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device | Unsoon Kim, Mark S. Chang, Yider Wu, Angela T. Hui, Yu Sun | 2003-01-21 |
| 6492675 | Flash memory array with dual function control lines and asymmetrical source and drain junctions | Michael A. Van Buskirk | 2002-12-10 |