Issued Patents All Time
Showing 51–75 of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6475847 | Method for forming a semiconductor device with self-aligned contacts using a liner oxide layer | Minh Van Ngo, Yu Sun, Fei Wang, Mark T. Ramsbey, Angela T. Hui +1 more | 2002-11-05 |
| 6469939 | Flash memory device with increase of efficiency during an APDE (automatic program disturb after erase) process | Zhigang Wang, Richard Fastow, Sheung-Hee Park, Sameer Haddad | 2002-10-22 |
| 6455373 | Semiconductor device having gate edges protected from charge gain/loss | Tuan Pham, Mark T. Ramsbey, Sameer Haddad, Angela T. Hui, Yu Sun | 2002-09-24 |
| 6444539 | Method for producing a shallow trench isolation filled with thermal oxide | Yu Sun, Angela T. Hui, Yue-Song He, Tatsuya Kajita, Mark S. Chang +1 more | 2002-09-03 |
| 6444530 | Process for fabricating an integrated circuit with a self-aligned contact | Hung-Sheng Chen, Unsoon Kim, Yu Sun, Mark T. Ramsbey, Mark Randolph +4 more | 2002-09-03 |
| 6429108 | Non-volatile memory device with encapsulated tungsten gate and method of making same | Richard J. Huang, Keizaburo Yoshie, Yu Sun | 2002-08-06 |
| 6420752 | Semiconductor device with self-aligned contacts using a liner oxide layer | Minh Van Ngo, Yu Sun, Fei Wang, Mark T. Ramsbey, Angela T. Hui +1 more | 2002-07-16 |
| 6399984 | Species implantation for minimizing interface defect density in flash memory devices | Yider Wu, Mark T. Ramsbey, Yu Sun, Tuan Pham, Jean Y. Yang | 2002-06-04 |
| 6381179 | Using a negative gate erase to increase the cycling endurance of a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure | Narbeh Derhacobian, Michael Van Buskirk, Daniel Sobek | 2002-04-30 |
| 6356482 | Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure | Narbeh Derhacobian, Michael Van Buskirk, Daniel Sobek | 2002-03-12 |
| 6346467 | Method of making tungsten gate MOS transistor and memory cell by encapsulating | Richard J. Huang, Keizaburo Yoshie, Yu Sun | 2002-02-12 |
| 6284600 | Species implantation for minimizing interface defect density in flash memory devices | Yider Wu, Mark T. Ramsbey, Yu Sun, Tuan Pham, Jean Y. Yang | 2001-09-04 |
| 6266281 | Method of erasing non-volatile memory cells | Narbeth Derhacobian, Michael A. Van Buskirk, Daniel Sobeck, Janet Wang | 2001-07-24 |
| 6266275 | Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for nand array flash memory | Paul L. Chen, Mike Van Buskirk, Shane Hollmer, Binh Quang Le, Shoichi Kawamura +3 more | 2001-07-24 |
| 6252803 | Automatic program disturb with intelligent soft programming for flash cells | Richard Fastow, Sameer Haddad, Lee Cleveland | 2001-06-26 |
| 6252276 | Non-volatile semiconductor memory device including assymetrically nitrogen doped gate oxide | Mark T. Ramsbey, Sameer Haddad, Vei-Han Chan, Yu Sun | 2001-06-26 |
| 6248627 | Method for protecting gate edges from charge gain/loss in semiconductor device | Tuan Pham, Mark T. Ramsbey, Sameer Haddad, Angela T. Hui, Yu Sun | 2001-06-19 |
| 6246610 | Symmetrical program and erase scheme to improve erase time degradation in NAND devices | K. Michael Han, Joseph G. Pawletko, Narbeh Derhacobian | 2001-06-12 |
| 6232646 | Shallow trench isolation filled with thermal oxide | Yu Sun, Angela T. Hui, Yue-Song He, Tatsuya Kajita, Mark S. Chang +1 more | 2001-05-15 |
| 6160317 | Method of spacer formation and source protection after self-aligned source formed and a device provided by such a method | Yu Sun, Mark T. Ramsbey | 2000-12-12 |
| 6080639 | Semiconductor device containing P-HDP interdielectric layer | Richard J. Huang | 2000-06-27 |
| 6001713 | Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device | Mark T. Ramsbey, Vei-Han Chan, Sameer Haddad, Yu Sun, Raymond Yu | 1999-12-14 |
| 6001689 | Process for fabricating a flash memory with dual function control lines | Michael A. Van Buskirk | 1999-12-14 |
| 5999452 | Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for NAND array flash memory | Pau-Ling Chen, Mike Van Buskirk, Shane Hollmer, Binh Quang Le, Shoichi Kawamura +3 more | 1999-12-07 |
| 5972751 | Methods and arrangements for introducing nitrogen into a tunnel oxide in a non-volatile semiconductor memory device | Mark T. Ramsbey, Sameer Haddad, Vei-Han Chan, Yu Sun | 1999-10-26 |