Issued Patents All Time
Showing 76–94 of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5966618 | Method of forming dual field isolation structures | Yu Sun, Tuan Pham, Mark T. Ramsbey | 1999-10-12 |
| 5933730 | Method of spacer formation and source protection after self-aligned source is formed and a device provided by such a method | Yu Sun, Mark T. Ramsbey | 1999-08-03 |
| 5912489 | Dual source side polysilicon select gate structure utilizing single tunnel oxide for NAND array flash memory | Pau-Ling Chen, Mike Van Buskirk, Shane Hollmer, Binh Quang Le, Shoichi Kawamura +3 more | 1999-06-15 |
| 5907781 | Process for fabricating an integrated circuit with a self-aligned contact | Hung-Sheng Chen, Unsoon Kim, Yu Sun, Mark T. Ramsbey, Mark Randolph +4 more | 1999-05-25 |
| 5856946 | Memory cell programming with controlled current injection | Vei-Han Chan, Sameer Haddad | 1999-01-05 |
| 5852582 | Non-volatile storage device refresh time detector | Lee Cleveland, Yuan Tang, Jonathan S. Su, Chung K. Chang | 1998-12-22 |
| 5805502 | System for constant field erasure in a FLASH EPROM | Yuan Tang, James Yu | 1998-09-08 |
| 5793677 | Using floating gate devices as select gate devices for NAND flash memory and its bias scheme | Chung-You Hu, Yu Sun, Sameer Haddad | 1998-08-11 |
| 5652155 | Method for making semiconductor circuit including non-ESD transistors with reduced degradation due to an impurity implant | David Kuan-Yu Liu, Ming Sang Kwan | 1997-07-29 |
| 5629893 | System for constant field erasure in a flash EPROM | Yuan Tang, James Yu | 1997-05-13 |
| 5596531 | Method for decreasing the discharge time of a flash EPROM cell | David Kuan-Yu Liu, Ming Sang Kwan, Sameer Haddad, Yuan Tang | 1997-01-21 |
| 5590076 | Channel hot-carrier page write | Sameer Haddad, David Kuan-Yu Liu | 1996-12-31 |
| 5517443 | Method and system for protecting a stacked gate edge in a semi-conductor device from self aligned source (SAS) etch in a semi-conductor device | David Kuan-Yu Liu, Yu Sun | 1996-05-14 |
| 5485423 | Method for eliminating of cycling-induced electron trapping in the tunneling oxide of 5 volt only flash EEPROMS | Yuan Tang, Michael A. Van Buskirk, Chung K. Chang | 1996-01-16 |
| 5470773 | Method protecting a stacked gate edge in a semiconductor device from self aligned source (SAS) etch | David Kuan-Yu Liu, Yu Sun | 1995-11-28 |
| 5457336 | Non-volatile memory structure including protection and structure for maintaining threshold stability | Hao Fang, Sameer Haddad | 1995-10-10 |
| 5335198 | Flash EEPROM array with high endurance | Michael A. Van Buskirk, Kevin W. Plouse, Joseph G. Pawletko, Sameer Haddad, Ravi Prakash Gutala | 1994-08-02 |
| 5077691 | Flash EEPROM array with negative gate voltage erase operation | Sameer Haddad, Antonio Matalvo, Michael A. Van Buskirk | 1991-12-31 |
| 4958321 | One transistor flash EPROM cell | — | 1990-09-18 |