Issued Patents 2023
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11830933 | Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up oxidation approach | Willy Rachmady, Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Patrick Morrow +2 more | 2023-11-28 |
| 11784239 | Subfin leakage suppression using fixed charge | Sean T. Ma, Aaron D. Lilak, Justin R. Weber, Harold W. Kennel, Willy Rachmady +5 more | 2023-10-10 |
| 11764263 | Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches | Ehren Mannebach, Anh Phan, Aaron D. Lilak, Willy Rachmady, Gilbert Dewey +3 more | 2023-09-19 |
| 11764104 | Forming an oxide volume within a fin | Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Ehren Mannebach, Patrick Morrow +3 more | 2023-09-19 |
| 11756998 | Source-channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs) | Tahir Ghani, Jack T. Kavalieros, Anand S. Murthy, Harold W. Kennel, Gilbert Dewey +4 more | 2023-09-12 |
| 11742346 | Interconnect techniques for electrically connecting source/drain regions of stacked transistors | Aaron D. Lilak, Gilbert Dewey, Christopher J. Jezewski, Ehren Mannebach, Rishabh Mehandru +4 more | 2023-08-29 |
| 11695081 | Channel layer formation for III-V metal-oxide-semiconductor field effect transistors (MOSFETs) | Sean T. Ma, Nicholas G. Minutillo, Tahir Ghani, Jack T. Kavalieros, Anand S. Murthy +4 more | 2023-07-04 |
| 11676966 | Stacked transistors having device strata with different channel widths | Gilbert Dewey, Jack T. Kavalieros, Willy Rachmady, Matthew V. Metz, Kimin Jun +4 more | 2023-06-13 |
| 11646352 | Stacked source-drain-gate connection and process for forming such | Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan +2 more | 2023-05-09 |
| 11640961 | III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts | Gilbert Dewey, Ravi Pillarisetty, Jack T. Kavalieros, Aaron D. Lilak, Willy Rachmady +6 more | 2023-05-02 |
| 11616056 | Vertical diode in stacked transistor architecture | Aaron D. Lilak, Patrick Morrow, Anh Phan, Rishabh Mehandru, Gilbert Dewey +1 more | 2023-03-28 |
| 11605565 | Three dimensional integrated circuits with stacked transistors | Willy Rachmady, Gilbert Dewey, Aaron D. Lilak, Kimin Jun, Brennen Mueller +5 more | 2023-03-14 |
| 11594533 | Stacked trigate transistors with dielectric isolation between first and second semiconductor fins | Willy Rachmady, Gilbert Dewey, Aaron D. Lilak, Patrick Morrow, Anh Phan +2 more | 2023-02-28 |
| 11573798 | Stacked transistors with different gate lengths in different device strata | Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Rishabh Mehandru, Ehren Mannebach +2 more | 2023-02-07 |
| 11569238 | Vertical memory cells | Aaron D. Lilak, Willy Rachmady, Gilbert Dewey, Kimin Jun, Hui Jae Yoo +5 more | 2023-01-31 |
| 11563119 | Etchstop regions in fins of semiconductor devices | Willy Rachmady, Gilbert Dewey, Erica J. Thompson, Aaron D. Lilak, Jack T. Kavalieros | 2023-01-24 |
| 11557658 | Transistors with high density channel semiconductor over dielectric material | Gilbert Dewey, Sean T. Ma, Tahir Ghani, Willy Rachmady, Anand S. Murthy +3 more | 2023-01-17 |
| 11552104 | Stacked transistors with dielectric between channels of different device strata | Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Rishabh Mehandru, Ehren Mannebach +3 more | 2023-01-10 |