Issued Patents 2021
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11004978 | Methods of forming doped source/drain contacts and structures formed thereby | Glenn A. Glass, Karthik Jambunathan, Chandra S. Mohapatra, Seiyon Kim | 2021-05-11 |
| 10998270 | Local interconnect for group IV source/drain regions | Seung Hoon Sung, Glenn A. Glass, Van H. Le, Ashish Agrawal, Benjamin Chu-Kung +1 more | 2021-05-04 |
| 10985263 | Thin film cap to lower leakage in low band gap material devices | Seung Hoon Sung, Dipanjan Basu, Ashish Agrawal, Van H. Le, Benjamin Chu-Kung +4 more | 2021-04-20 |
| 10978568 | Passivation of transistor channel region interfaces | Glenn A. Glass, Mark R. Brazier, Tahir Ghani, Owen Loh | 2021-04-13 |
| 10957796 | Semiconductor device having doped epitaxial region and its methods of fabrication | Daniel Bourne Aubertine, Tahir Ghani, Abhijit Jayant Pethe | 2021-03-23 |
| 10957769 | High-mobility field effect transistors with wide bandgap fin cladding | Sean T. Ma, Chandra S. Mohapatra, Gilbert Dewey, Willy Rachmady, Harold W. Kennel +3 more | 2021-03-23 |
| 10944006 | Geometry tuning of fin based transistor | Glenn A. Glass, Karthik Jambunathan, Chandra S. Mohapatra, Hei Kam, Nabil G. Mistkawi +2 more | 2021-03-09 |
| 10903364 | Semiconductor device with released source and drain | Willy Rachmady, Sanaz K. Gardner, Chandra S. Mohapatra, Matthew V. Metz, Gilbert Dewey +3 more | 2021-01-26 |
| 10892337 | Backside source/drain replacement for semiconductor devices with metallization on both sides | Glenn A. Glass, Karthik Jambunathan, Chandra S. Mohapatra, Patrick Morrow, Mauro J. Kobrinsky | 2021-01-12 |
| 10892335 | Device isolation by fixed charge | Sean T. Ma, Willy Rachmady, Gilbert Dewey, Aaron D. Lilak, Justin R. Weber +5 more | 2021-01-12 |
| 10886408 | Group III-V material transistors employing nitride-based dopant diffusion barrier layer | Chandra S. Mohapatra, Harold W. Kennel, Glenn A. Glass, Willy Rachmady, Gilbert Dewey +4 more | 2021-01-05 |
| 10886272 | Techniques for forming dual-strain fins for co-integrated n-MOS and p-MOS devices | Stephen M. Cea, Rishabh Mehandru, Anupama Bowonder, Tahir Ghani | 2021-01-05 |