Issued Patents 2021
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11205707 | Optimizing gate profile for performance and gate fill | Nadia M. Rahhal-Orabi, Tahir Ghani, Willy Rachmady, Jack T. Kavalieros, Gilbert Dewey +2 more | 2021-12-21 |
| 11195924 | Broken bandgap contact | Benjamin Chu-Kung, Van H. Le, Jack T. Kavalieros, Willy Rachmady, Ashish Agrawal +1 more | 2021-12-07 |
| 11177255 | Transistor structures having multiple threshold voltage channel materials | Sean T. Ma, Willy Rachmady, Gilbert Dewey, Harold W. Kennel, Cheng-Ying Huang +3 more | 2021-11-16 |
| 11171207 | Transistor with isolation below source and drain | Willy Rachmady, Cheng-Ying Huang, Nicholas G. Minutillo, Sean T. Ma, Anand S. Murthy +3 more | 2021-11-09 |
| 11164747 | Group III-V semiconductor devices having asymmetric source and drain structures | Sean T. Ma, Gilbert Dewey, Willy Rachmady, Harold W. Kennel, Cheng-Ying Huang +3 more | 2021-11-02 |
| 11164974 | Channel layer formed in an art trench | Willy Rachmady, Gilbert Dewey, Nancy Zelick, Harold W. Kennel, Nicholas G. Minutillo +1 more | 2021-11-02 |
| 11152290 | Wide bandgap group IV subfin to reduce leakage | Benjamin Chu-Kung, Van H. Le, Willy Rachmady, Jack T. Kavalieros, Ashish Agrawal +1 more | 2021-10-19 |
| 11107890 | FINFET transistor having a doped subfin structure to reduce channel to substrate leakage | Gilbert Dewey, Willy Rachmady, Anand S. Murthy, Chandra S. Mohapatra, Tahir Ghani +2 more | 2021-08-31 |
| 11049773 | Art trench spacers to enable fin release for non-lattice matched channels | Gilbert Dewey, Sean T. Ma, Cheng-Ying Huang, Tahir Ghani, Anand S. Murthy +4 more | 2021-06-29 |
| 11031482 | Gate electrode having a capping layer | Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask | 2021-06-08 |
| 11031499 | Germanium transistor structure with underlap tip to reduce gate induced barrier lowering/short channel effect while minimizing impact on drive current | Willy Rachmady, Van H. Le, Benjamin Chu-Kung, Ashish Agrawal, Jack T. Kavalieros | 2021-06-08 |
| 11017843 | Thin film transistors for memory cell array layer selection | Abhishek A. Sharma, Gilbert Dewey, Willy Rachmady, Van H. Le, Jack T. Kavalieros | 2021-05-25 |
| 10957769 | High-mobility field effect transistors with wide bandgap fin cladding | Sean T. Ma, Chandra S. Mohapatra, Gilbert Dewey, Willy Rachmady, Harold W. Kennel +3 more | 2021-03-23 |
| 10937907 | Method for fabricating transistor with thinned channel | Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle +3 more | 2021-03-02 |
| 10930766 | Ge NANO wire transistor with GAAS as the sacrificial layer | Willy Rachmady, Van H. Le, Jack T. Kavalieros, Sanaz K. Gardner | 2021-02-23 |
| 10903364 | Semiconductor device with released source and drain | Willy Rachmady, Sanaz K. Gardner, Chandra S. Mohapatra, Gilbert Dewey, Sean T. Ma +3 more | 2021-01-26 |
| 10892335 | Device isolation by fixed charge | Sean T. Ma, Willy Rachmady, Gilbert Dewey, Aaron D. Lilak, Justin R. Weber +5 more | 2021-01-12 |
| 10886408 | Group III-V material transistors employing nitride-based dopant diffusion barrier layer | Chandra S. Mohapatra, Harold W. Kennel, Glenn A. Glass, Willy Rachmady, Anand S. Murthy +4 more | 2021-01-05 |