Issued Patents 2021
Showing 25 most recent of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11194578 | Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor | Steven J. Battle, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard +2 more | 2021-12-07 |
| 11188340 | Multiple streams execution for hard-to-predict branches in a microprocessor | Brian W. Thompto, Hung Q. Le | 2021-11-30 |
| 11188332 | System and handling of register data in processors | Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen +2 more | 2021-11-30 |
| 11182164 | Pairing issue queues for complex instructions and instruction fusion | Brian D. Barrick, John B. Griswell, Jr., Brian W. Thompto | 2021-11-23 |
| 11163571 | Fusion to enhance early address generation of load instructions in a microprocessor | Brian D. Barrick, Sundeep Chadha, Sheldon B. Levenstein, Phillip G. Williams, Niels Fricke +2 more | 2021-11-02 |
| 11163568 | Implementing write ports in register-file array cell | Saiful Islam, Sam Gat-Shang Chu, Binglong Zhang, Howard Levy, David R. Terry +1 more | 2021-11-02 |
| 11157276 | Thread-based organization of slice target register file entry in a microprocessor to permit writing scalar or vector data to portions of a single register file entry | Steven J. Battle, Maarten J. Boersma, Niels Fricke, Hung Q. Le, Brian W. Thompto | 2021-10-26 |
| 11150909 | Energy efficient source operand issue | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney | 2021-10-19 |
| 11150907 | Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries | Salma Ayub, Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le +1 more | 2021-10-19 |
| 11144323 | Independent mapping of threads | Sam Gat-Shang Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira +1 more | 2021-10-12 |
| 11144364 | Supporting speculative microprocessor instruction execution | Steven J. Battle, Brandon Goddard, Joshua W. Bowman, Brian D. Barrick, Susan E. Eisen +2 more | 2021-10-12 |
| 11144319 | Redistribution of architected states for a processor register file | Steven J. Battle, Susan E. Eisen, Salma Ayub, Albert J. Van Norstrand, Jr., Kent Li +2 more | 2021-10-12 |
| 11138050 | Operation of a multi-slice processor implementing a hardware level transfer of an execution thread | Brian D. Barrick, James Wilson Bishop, Marcy E. Byers, Sundeep Chadha, Cliff Kucharski +2 more | 2021-10-05 |
| 11132198 | Instruction handling for accumulation of register results in a microprocessor | Brian W. Thompto, Maarten J. Boersma, Andreas Wagner, Jose E. Moreira, Hung Q. Le +1 more | 2021-09-28 |
| 11119772 | Check pointing of accumulator register results in a microprocessor | Steven J. Battle, Brian D. Barrick, Susan E. Eisen, Andreas Wagner, Brian W. Thompto +2 more | 2021-09-14 |
| 11119774 | Slice-target register file for microprocessor | Brian W. Thompto, Hung Q. Le, Sam Gat-Shang Chu | 2021-09-14 |
| 11106466 | Decoupling of conditional branches | Nicholas R. Orzol, Michael J. Genden, Hung Q. Le, Eula Faye Abalos Tolentino, Brian W. Thompto | 2021-08-31 |
| 11093246 | Banked slice-target register file for wide dataflow execution in a microprocessor | Maarten J. Boersma, Niels Fricke, Michael K. Kroener, Hung Q. Le, Brian W. Thompto | 2021-08-17 |
| 11093282 | Register file write using pointers | Brian D. Barrick, Steven J. Battle, Joshua W. Bowman, Cliff Kucharski, Hung Q. Le +1 more | 2021-08-17 |
| 11068267 | High bandwidth logical register flush recovery | Steven J. Battle, Brandon Goddard, Joshua W. Bowman, Brian D. Barrick, Susan E. Eisen +2 more | 2021-07-20 |
| 11068274 | Prioritized instructions in an instruction completion table of a simultaneous multithreading processor | Kenneth L. Ward, Susan E. Eisen, Albert J. Van Norstrand, Jr., Glenn O. Kincaid, Christopher M. Mueller | 2021-07-20 |
| 11061681 | Instruction streaming using copy select vector | Steven J. Battle, Joshua W. Bowman, Hung Q. Le, Brian W. Thompto | 2021-07-13 |
| 11030018 | On-demand multi-tiered hang buster for SMT microprocessor | Steven J. Battle, Susan E. Eisen, Kenneth L. Ward, Eula Faye Abalos Tolentino, Cliff Kucharski +2 more | 2021-06-08 |
| 10996995 | Saving and restoring a transaction memory state | Steven J. Battle, Hung Q. Le, James Wilson Bishop, Brian W. Thompto, Susan E. Eisen | 2021-05-04 |
| 10983797 | Program instruction scheduling | Christian Zoellin, Phillip G. Williams, Brian W. Thompto, Hung Q. Le, Jessica Hui-Chun Tseng +3 more | 2021-04-20 |