Issued Patents 2021
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11188340 | Multiple streams execution for hard-to-predict branches in a microprocessor | Hung Q. Le, Dung Q. Nguyen | 2021-11-30 |
| 11188328 | Compute array of a processor with mixed-precision numerical linear algebra support | Jose E. Moreira, Brett Olsson, Silvia M. Mueller, Andreas Wagner | 2021-11-30 |
| 11182164 | Pairing issue queues for complex instructions and instruction fusion | Brian D. Barrick, John B. Griswell, Jr., Dung Q. Nguyen | 2021-11-23 |
| 11182458 | Three-dimensional lane predication for matrix operations | Brett Olsson, Jose E. Moreira, Silvia M. Mueller, Andreas Wagner | 2021-11-23 |
| 11163571 | Fusion to enhance early address generation of load instructions in a microprocessor | Brian D. Barrick, Sundeep Chadha, Sheldon B. Levenstein, Phillip G. Williams, Niels Fricke +2 more | 2021-11-02 |
| 11163695 | Methods and systems for translating virtual addresses in a virtual memory based system | Mohit Karve | 2021-11-02 |
| 11163577 | Selectively supporting static branch prediction settings only in association with processor-designated types of instructions | Sheldon B. Levenstein, David S. Levitan | 2021-11-02 |
| 11157276 | Thread-based organization of slice target register file entry in a microprocessor to permit writing scalar or vector data to portions of a single register file entry | Steven J. Battle, Maarten J. Boersma, Niels Fricke, Hung Q. Le, Dung Q. Nguyen | 2021-10-26 |
| 11150907 | Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries | Salma Ayub, Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le +1 more | 2021-10-19 |
| 11144323 | Independent mapping of threads | Sam Gat-Shang Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira +1 more | 2021-10-12 |
| 11138089 | Performance benchmark generation | Shricharan Srivatsan, Vivek Britto, Aishwarya Dhandapani, Tharunachalam Pindicura, John A. Schumann | 2021-10-05 |
| 11132198 | Instruction handling for accumulation of register results in a microprocessor | Maarten J. Boersma, Andreas Wagner, Jose E. Moreira, Hung Q. Le, Silvia M. Mueller +1 more | 2021-09-28 |
| 11119772 | Check pointing of accumulator register results in a microprocessor | Steven J. Battle, Brian D. Barrick, Susan E. Eisen, Andreas Wagner, Dung Q. Nguyen +2 more | 2021-09-14 |
| 11119774 | Slice-target register file for microprocessor | Dung Q. Nguyen, Hung Q. Le, Sam Gat-Shang Chu | 2021-09-14 |
| 11119932 | Operation of a multi-slice processor implementing adaptive prefetch control | Bradly G. Frey, George W. Rohrbaugh, III | 2021-09-14 |
| 11106466 | Decoupling of conditional branches | Nicholas R. Orzol, Michael J. Genden, Hung Q. Le, Dung Q. Nguyen, Eula Faye Abalos Tolentino | 2021-08-31 |
| 11093248 | Prefetch queue allocation protection bubble in a processor | Vivek Britto, Mohit Karve, George W. Rohrbaugh, III | 2021-08-17 |
| 11093246 | Banked slice-target register file for wide dataflow execution in a microprocessor | Maarten J. Boersma, Niels Fricke, Michael K. Kroener, Hung Q. Le, Dung Q. Nguyen | 2021-08-17 |
| 11080060 | Preventing operand store compare conflicts using conflict address data tables | Ehsan Fatehi, John B. Griswell, Jr. | 2021-08-03 |
| 11061681 | Instruction streaming using copy select vector | Steven J. Battle, Joshua W. Bowman, Hung Q. Le, Dung Q. Nguyen | 2021-07-13 |
| 10996995 | Saving and restoring a transaction memory state | Steven J. Battle, Dung Q. Nguyen, Hung Q. Le, James Wilson Bishop, Susan E. Eisen | 2021-05-04 |
| 10983800 | Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti +1 more | 2021-04-20 |
| 10983797 | Program instruction scheduling | Christian Zoellin, Phillip G. Williams, Dung Q. Nguyen, Hung Q. Le, Jessica Hui-Chun Tseng +3 more | 2021-04-20 |
| 10963249 | Processor prefetcher mode governor for switching between prefetch modes | Mohit Karve, Vivek Britto, George W. Rohrbaugh, III | 2021-03-30 |
| 10949205 | Implementation of execution compression of instructions in slice target register file mapper | Joshua W. Bowman, Dung Q. Nguyen, Hung Q. Le, Maureen A. Delaney, Cliff Kucharski +1 more | 2021-03-16 |