Issued Patents 2021
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11194578 | Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor | Steven J. Battle, Brian D. Barrick, Joshua W. Bowman, Brandon Goddard, Cliff Kucharski +2 more | 2021-12-07 |
| 11188332 | System and handling of register data in processors | Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Brandon Goddard +2 more | 2021-11-30 |
| 11144364 | Supporting speculative microprocessor instruction execution | Steven J. Battle, Brandon Goddard, Dung Q. Nguyen, Joshua W. Bowman, Brian D. Barrick +2 more | 2021-10-12 |
| 11144319 | Redistribution of architected states for a processor register file | Steven J. Battle, Dung Q. Nguyen, Salma Ayub, Albert J. Van Norstrand, Jr., Kent Li +2 more | 2021-10-12 |
| 11119772 | Check pointing of accumulator register results in a microprocessor | Steven J. Battle, Brian D. Barrick, Andreas Wagner, Dung Q. Nguyen, Brian W. Thompto +2 more | 2021-09-14 |
| 11086630 | Finish exception handling of an instruction completion table | Kenneth L. Ward, Christopher M. Mueller, Glenn O. Kincaid, Dhivya Jeganathan | 2021-08-10 |
| 11068274 | Prioritized instructions in an instruction completion table of a simultaneous multithreading processor | Kenneth L. Ward, Dung Q. Nguyen, Albert J. Van Norstrand, Jr., Glenn O. Kincaid, Christopher M. Mueller | 2021-07-20 |
| 11068267 | High bandwidth logical register flush recovery | Steven J. Battle, Brandon Goddard, Dung Q. Nguyen, Joshua W. Bowman, Brian D. Barrick +2 more | 2021-07-20 |
| 11030018 | On-demand multi-tiered hang buster for SMT microprocessor | Steven J. Battle, Dung Q. Nguyen, Kenneth L. Ward, Eula Faye Abalos Tolentino, Cliff Kucharski +2 more | 2021-06-08 |
| 10996995 | Saving and restoring a transaction memory state | Steven J. Battle, Dung Q. Nguyen, Hung Q. Le, James Wilson Bishop, Brian W. Thompto | 2021-05-04 |
| 10977034 | Instruction completion table with ready-to-complete vector | Kenneth L. Ward, Glenn O. Kincaid, Dung Q. Nguyen, Deepak Singh, Gaurav Mittal +1 more | 2021-04-13 |
| 10956158 | System and handling of register data in processors | Steven J. Battle, Khandker N. Adeeb, Brian D. Barrick, Joshua W. Bowman, Thao T. Doan +2 more | 2021-03-23 |
| 10949213 | Logical register recovery within a processor | Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Brandon Goddard +2 more | 2021-03-16 |
| 10901743 | Speculative execution of both paths of a weakly predicted branch instruction | Kenneth L. Ward, Dung Q. Nguyen, Hung Q. Le | 2021-01-26 |