| 11119772 |
Check pointing of accumulator register results in a microprocessor |
Steven J. Battle, Brian D. Barrick, Susan E. Eisen, Andreas Wagner, Dung Q. Nguyen +2 more |
2021-09-14 |
| 11086630 |
Finish exception handling of an instruction completion table |
Susan E. Eisen, Christopher M. Mueller, Glenn O. Kincaid, Dhivya Jeganathan |
2021-08-10 |
| 11068274 |
Prioritized instructions in an instruction completion table of a simultaneous multithreading processor |
Susan E. Eisen, Dung Q. Nguyen, Albert J. Van Norstrand, Jr., Glenn O. Kincaid, Christopher M. Mueller |
2021-07-20 |
| 11030018 |
On-demand multi-tiered hang buster for SMT microprocessor |
Steven J. Battle, Dung Q. Nguyen, Susan E. Eisen, Eula Faye Abalos Tolentino, Cliff Kucharski +2 more |
2021-06-08 |
| 10977034 |
Instruction completion table with ready-to-complete vector |
Susan E. Eisen, Glenn O. Kincaid, Dung Q. Nguyen, Deepak Singh, Gaurav Mittal +1 more |
2021-04-13 |
| 10929144 |
Speculatively releasing store data before store instruction completion in a processor |
Hung Q. Le, Dung Q. Nguyen, Bryan Lloyd |
2021-02-23 |
| 10901743 |
Speculative execution of both paths of a weakly predicted branch instruction |
Dung Q. Nguyen, Susan E. Eisen, Hung Q. Le |
2021-01-26 |
