| 11194578 |
Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor |
Steven J. Battle, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard +2 more |
2021-12-07 |
| 11188332 |
System and handling of register data in processors |
Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen +2 more |
2021-11-30 |
| 11144364 |
Supporting speculative microprocessor instruction execution |
Steven J. Battle, Brandon Goddard, Dung Q. Nguyen, Joshua W. Bowman, Brian D. Barrick +2 more |
2021-10-12 |
| 11138050 |
Operation of a multi-slice processor implementing a hardware level transfer of an execution thread |
Brian D. Barrick, James Wilson Bishop, Marcy E. Byers, Sundeep Chadha, Dung Q. Nguyen +2 more |
2021-10-05 |
| 11093282 |
Register file write using pointers |
Brian D. Barrick, Steven J. Battle, Joshua W. Bowman, Hung Q. Le, Dung Q. Nguyen +1 more |
2021-08-17 |
| 11030018 |
On-demand multi-tiered hang buster for SMT microprocessor |
Steven J. Battle, Dung Q. Nguyen, Susan E. Eisen, Kenneth L. Ward, Eula Faye Abalos Tolentino +2 more |
2021-06-08 |
| 10949205 |
Implementation of execution compression of instructions in slice target register file mapper |
Joshua W. Bowman, Dung Q. Nguyen, Hung Q. Le, Brian W. Thompto, Maureen A. Delaney +1 more |
2021-03-16 |
