| 11194575 |
Instruction address based data prediction and prefetching |
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| 11182161 |
Fractional or partial line usage prediction in a processor |
Edmund J. Gieske, Naga P. Gorti |
2021-11-23 |
| 11163695 |
Methods and systems for translating virtual addresses in a virtual memory based system |
Brian W. Thompto |
2021-11-02 |
| 11163683 |
Dynamically adjusting prefetch depth |
Edmund J. Gieske, Vivek Britto, George W. Rohrbaugh, III |
2021-11-02 |
| 11151054 |
Speculative address translation requests pertaining to instruction cache misses |
Naga P. Gorti |
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| 11093248 |
Prefetch queue allocation protection bubble in a processor |
Vivek Britto, George W. Rohrbaugh, III, Brian W. Thompto |
2021-08-17 |
| 11016900 |
Limiting table-of-contents prefetching consequent to symbol table requests |
Edmund J. Gieske |
2021-05-25 |
| 10963249 |
Processor prefetcher mode governor for switching between prefetch modes |
Vivek Britto, George W. Rohrbaugh, III, Brian W. Thompto |
2021-03-30 |
| 10942747 |
Head and tail pointer manipulation in a first-in-first-out issue queue |
Joel A. Silberman, Balaram Sinharoy |
2021-03-09 |
| 10922087 |
Block based allocation and deallocation of issue queue entries |
Joel A. Silberman, Balaram Sinharoy |
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| 10915446 |
Prefetch confidence and phase prediction for improving prefetch performance in bandwidth constrained scenarios |
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| 10901744 |
Buffered instruction dispatching to an issue queue |
Joel A. Silberman, Balaram Sinharoy |
2021-01-26 |
