Issued Patents 2020
Showing 151–175 of 332 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10680064 | Techniques for VFET top source/drain epitaxy | Cheng Chi, Chi-Chun Liu, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2020-06-09 |
| 10680063 | Method of manufacturing stacked SiGe nanotubes | Juntao Li, Choonghyun Lee | 2020-06-09 |
| 10680000 | Vertical field effect transistor including integrated antifuse | Juntao Li, Geng Wang, Qintao Zhang | 2020-06-09 |
| 10679998 | Vertical field effect transistor including integrated antifuse | Juntao Li, Geng Wang, Qintao Zhang | 2020-06-09 |
| 10679992 | Integrated device with vertical field-effect transistors and hybrid channels | Zhenxing Bi, Zheng Xu, Dexin Kong | 2020-06-09 |
| 10679939 | Electrical fuse and/or resistor structures | Veeraraghavan S. Basker, Ali Khakifirooz, Juntao Li | 2020-06-09 |
| 10679894 | Airgap spacers formed in conjunction with a late gate cut | Julien Frougier, Ruilong Xie, Chanro Park | 2020-06-09 |
| 10672887 | Vertical FET with shaped spacer to reduce parasitic capacitance | Junli Wang, Theodorus E. Standaert, Veeraraghavan S. Basker | 2020-06-02 |
| 10669579 | DNA sequencing with stacked nanopores | Zhenxing Bi, Juntao Li, Xin Miao | 2020-06-02 |
| 10672888 | Vertical transistors having improved gate length control | Xin Miao, Wenyu Xu, Chen Zhang | 2020-06-02 |
| 10672862 | High density vertically integrated FEOL MIM capacitor | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2020-06-02 |
| 10665692 | Non-self aligned gate contacts formed over the active region of a transistor | Ruilong Xie, Chanro Park, Julien Frougier | 2020-05-26 |
| 10665414 | Piezoelectric vacuum transistor | Qing Cao, Zhengwen Li, Fei Liu | 2020-05-26 |
| 10665505 | Self-aligned gate contact isolation | Peng Xu, Ekmini Anuja De Silva, Ruilong Xie | 2020-05-26 |
| 10665511 | Self-limiting liners for increasing contact trench volume in N-type and P-type transistors | Choonghyun Lee, Juntao Li, Peng Xu | 2020-05-26 |
| 10665512 | Stress modulation of nFET and pFET fin structures | Huimei Zhou, Michael P. Belyansky, Oleg Gluschenkov, Richard A. Conti, James J. Kelly +1 more | 2020-05-26 |
| 10665666 | Method of forming III-V on insulator structure on semiconductor substrate | Xin Miao, Wenyu Xu, Chen Zhang | 2020-05-26 |
| 10665694 | Vertical transistors having improved gate length control | Xin Miao, Wenyu Xu, Chen Zhang | 2020-05-26 |
| 10665698 | Reducing gate-induced-drain-leakage current in a transistor by forming an enhanced band gap layer at the channel-to-drain interface | Choonghyun Lee, Juntao Li, Shogo Mochizuki | 2020-05-26 |
| 10665714 | Vertical transistors with various gate lengths | Juntao Li, Choonghyun Lee, Shogo Mochizuki | 2020-05-26 |
| 10665783 | Nanoparticle with plural functionalities, and method of forming the nanoparticle | Qing Cao, Zhengwen Li, Fei Liu | 2020-05-26 |
| 10658246 | Self-aligned vertical fin field effect transistor with replacement gate structure | Chen Zhang, Tenko Yamashita, Xin Miao, Juntao Li | 2020-05-19 |
| 10658590 | Techniques for forming RRAM cells | Juntao Li, Dexin Kong, Takashi Ando | 2020-05-19 |
| 10658583 | Forming RRAM cell structure with filament confinement | Juntao Li, Dexin Kong, Takashi Ando | 2020-05-19 |
| 10658507 | Vertical transistor pass gate device | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2020-05-19 |