Issued Patents 2018
Showing 76–100 of 171 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9997453 | Antifuse having comb-like top electrode | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2018-06-12 |
| 9997619 | Bipolar junction transistors and methods forming same | Karthik Balakrishnan, Bahman Hekmatshoartabari, Jeng-Bang Yau | 2018-06-12 |
| 9997590 | FinFET resistor and method to fabricate same | Praneet Adusumilli, Keith E. Fogel, Oscar van der Straten | 2018-06-12 |
| 9997540 | Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Kern Rim | 2018-06-12 |
| 9997407 | Voidless contact metal structures | Veeraraghavan S. Basker, Nicolas L. Breil, Oleg Gluschenkov, Shogo Mochizuki | 2018-06-12 |
| 9991166 | Wimpy device by selective laser annealing | Kangguo Cheng, Nicolas Loubet, Xin Miao | 2018-06-05 |
| 9991382 | Vertical field effect transistor with abrupt extensions at a bottom source/drain structure | Shogo Mochizuki | 2018-06-05 |
| 9991359 | Vertical transistor gated diode | Karthik Balakrishnan | 2018-06-05 |
| 9991168 | Germanium dual-fin field effect transistor | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-06-05 |
| 9985024 | Minimizing shorting between FinFET epitaxial regions | Kangguo Cheng, Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2018-05-29 |
| 9984871 | Superlattice lateral bipolar junction transistor | Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari | 2018-05-29 |
| 9985114 | Fin field effect transistor structure and method to form defect free merged source and drain epitaxy for low external resistance | Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki | 2018-05-29 |
| 9978775 | FinFET device with abrupt junctions | Kangguo Cheng, Hong He, Ali Khakifirooz, Soon-Cheon Seo | 2018-05-22 |
| 9978748 | Method of cutting fins to create diffusion breaks for finFETs | Hemanth Jagannathan, Sivananda K. Kanakasabapathy | 2018-05-22 |
| 9972620 | Preventing shorting between source and/or drain contacts and gate | Charan V. Surisetty, Dominic J. Schepis, Kangguo Cheng | 2018-05-15 |
| 9972711 | Reduced resistance short-channel InGaAs planar MOSFET | Pranita Kerber, Qiqing C. Ouyang | 2018-05-15 |
| 9972684 | Compressive strain semiconductor substrates | Karthik Balakrishnan, Pouya Hashemi, Nicolas Loubet | 2018-05-15 |
| 9966374 | Semiconductor device with gate structures having low-K spacers on sidewalls and electrical contacts therebetween | Kangguo Cheng, Ali Khakifirooz, Charan V. Surisetty | 2018-05-08 |
| 9966457 | Transistor structure with varied gate cross-sectional area | Dominic J. Schepis, Pranita Kerber, Qiqing C. Ouyang | 2018-05-08 |
| 9966387 | Strain release in pFET regions | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Kern Rim | 2018-05-08 |
| 9960240 | Low resistance contact structures for trench structures | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2018-05-01 |
| 9953973 | Diode connected vertical transistor | Karthik Balakrishnan, Pouya Hashemi | 2018-04-24 |
| 9954116 | Electrostatically enhanced fins field effect transistors | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz | 2018-04-24 |
| 9954106 | III-V fin on insulator | Kangguo Cheng, Hemanth Jagannathan | 2018-04-24 |
| 9954103 | Bottom spacer formation for vertical transistor | Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki | 2018-04-24 |