Issued Patents 2018
Showing 126–150 of 171 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9922886 | Silicon-germanium FinFET device with controlled junction | Kangguo Cheng, Pouya Hashemi, Kam-Leung Lee | 2018-03-20 |
| 9917177 | Contact structure and extension formation for III-V nFET | Veeraraghavan S. Basker | 2018-03-13 |
| 9917200 | Nanowire transistor structures with merged source/drain regions using auxiliary pillars | Pouya Hashemi, Ali Khakifirooz | 2018-03-13 |
| 9917179 | Stacked nanowire devices formed using lateral aspect ratio trapping | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-03-13 |
| 9917175 | Tapered vertical FET having III-V channel | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-03-13 |
| 9917089 | III-V semiconductor CMOS FinFET device | Hemanth Jagannathan, Devendra K. Sadana, Charan V. Surisetty | 2018-03-13 |
| 9917015 | Dual channel material for finFET for high performance CMOS | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz | 2018-03-13 |
| 9911739 | III-V FinFET CMOS with III-V and germanium-containing channel closely spaced | Kangguo Cheng, Ali Khakifirooz, Ghavam G. Shahidi | 2018-03-06 |
| 9911849 | Transistor and method of forming same | Veeraraghavan S. Basker, Nicolas L. Breil, Oleg Gluschenkov, Shogo Mochizuki | 2018-03-06 |
| 9911741 | Dual channel material for finFET for high performance CMOS | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz | 2018-03-06 |
| 9911662 | Forming a CMOS with dual strained channels | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz | 2018-03-06 |
| 9911656 | Wimpy device by selective laser annealing | Kangguo Cheng, Nicolas Loubet, Xin Miao | 2018-03-06 |
| 9905649 | Tensile strained nFET and compressively strained pFET formed on strain relaxed buffer | Karthik Balakrishnan, Keith E. Fogel, Pouya Hashemi | 2018-02-27 |
| 9905692 | SOI FinFET fins with recessed fins and epitaxy in source drain region | Shogo Mochizuki, Veeraraghavan S. Basker, Nicolas L. Breil, Oleg Gluschenkov | 2018-02-27 |
| 9899378 | Simultaneously fabricating a high voltage transistor and a finFET | Kangguo Cheng, Ali Khakifirooz, Charan V. Surisetty | 2018-02-20 |
| 9899495 | Vertical transistors with reduced bottom electrode series resistance | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-02-20 |
| 9899384 | Self aligned structure and method for high-K metal gate work function tuning | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz | 2018-02-20 |
| 9899274 | Low-cost SOI FinFET technology | Stephen W. Bedell, Joel P. de Souza, Devendra K. Sadana, Dominic J. Schepis | 2018-02-20 |
| 9892975 | Adjacent strained <100> NFET fins and <110> PFET fins | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi | 2018-02-13 |
| 9893207 | Programmable read only memory (ROM) integrated in tight pitch vertical transistor structures | Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning | 2018-02-13 |
| 9893151 | Method and apparatus providing improved thermal conductivity of strain relaxed buffer | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-02-13 |
| 9893014 | Designable channel FinFET fuse | Keith E. Fogel, Pouya Hashemi, Shogo Mochizuki | 2018-02-13 |
| 9892978 | Forming a CMOS with dual strained channels | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz | 2018-02-13 |
| 9892925 | Overhang hardmask to prevent parasitic epitaxial nodules at gate end during source drain epitaxy | Kangguo Cheng, Pouya Hashemi, Shogo Mochizuki | 2018-02-13 |
| 9887197 | Structure containing first and second vertically stacked nanosheets having different crystallographic orientations | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-02-06 |