Issued Patents 2018
Showing 101–125 of 171 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9954102 | Vertical field effect transistor with abrupt extensions at a bottom source/drain structure | Shogo Mochizuki | 2018-04-24 |
| 9954083 | Semiconductor structures having increased channel strain using fin release in gate regions | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Kern Rim | 2018-04-24 |
| 9954058 | Self-aligned air gap spacer for nanosheet CMOS devices | Shogo Mochizuki, Joshua M. Rubin, Junli Wang | 2018-04-24 |
| 9954050 | Precise/designable FinFET resistor structure | Praneet Adusumilli, Shanti Pancharatnam, Oscar van der Straten | 2018-04-24 |
| 9953884 | Field effect transistor including strained germanium fins | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-04-24 |
| 9947621 | Structure and method to reduce copper loss during metal cap formation | Praneet Adusumilli, Oscar van der Straten | 2018-04-17 |
| 9947778 | Lateral bipolar junction transistor with controlled junction | Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning | 2018-04-17 |
| 9947775 | Replacement III-V or germanium nanowires by unilateral confined epitaxial growth | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-04-17 |
| 9947689 | Semiconductor device structure with 110-PFET and 111-NFET current flow direction | Pouya Hashemi, Ali Khakifirooz, Shogo Mochizuki | 2018-04-17 |
| 9947675 | Mask-programmable ROM using a vertical FET integration process | Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning | 2018-04-17 |
| 9947649 | Large area electrostatic dischage for vertical transistor structures | Karthik Balakrishnan, Pouya Hashemi, Jeng-Bang Yau | 2018-04-17 |
| 9947532 | Forming zig-zag trench structure to prevent aspect ratio trapping defect escape | Judson R. Holt, Shogo Mochizuki, Melissa A. Smith | 2018-04-17 |
| 9941302 | Structure and method to form defect free high-mobility semiconductor fins on insulator | Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki | 2018-04-10 |
| 9941391 | Method of forming vertical transistor having dual bottom spacers | Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki | 2018-04-10 |
| 9941370 | Vertical field-effect-transistors having multiple threshold voltages | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-04-10 |
| 9941204 | III-V compatible anti-fuses | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2018-04-10 |
| 9935051 | Multi-level metallization interconnect structure | Praneet Adusumilli, Oscar van der Straten | 2018-04-03 |
| 9935186 | Method of manufacturing SOI lateral Si-emitter SiGe base HBT | Pouya Hashemi, Tak H. Ning | 2018-04-03 |
| 9935185 | Superlattice lateral bipolar junction transistor | Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari | 2018-04-03 |
| 9935181 | FinFET having highly doped source and drain regions | Kangguo Cheng, Ali Khakifirooz, Dominic J. Schepis | 2018-04-03 |
| 9934977 | Salicide bottom contacts | Praneet Adusumilli, Oscar van der Straten | 2018-04-03 |
| 9929270 | Gate all-around FinFET device and a method of manufacturing same | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-03-27 |
| 9929266 | Method and structure for incorporating strain in nanosheet devices | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-03-27 |
| 9922941 | Thin low defect relaxed silicon germanium layers on bulk silicon substrates | Praneet Adusumilli, Keith E. Fogel, Oscar van der Straten | 2018-03-20 |
| 9923084 | Forming a fin using double trench epitaxy | Veeraraghavan S. Basker, Pouya Hashemi, Shogo Mochizuki | 2018-03-20 |