Issued Patents 2018
Showing 51–75 of 171 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10056254 | Methods for removal of selected nanowires in stacked gate all around architecture | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-08-21 |
| 10049945 | Forming a CMOS with dual strained channels | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz | 2018-08-14 |
| 10049980 | Low resistance seed enhancement spacers for voidless interconnect structures | Praneet Adusumilli, Joseph F. Maniscalco, Oscar van der Straten | 2018-08-14 |
| 10050143 | Integrated ferroelectric capacitor/ field effect transistor structure | Takashi Ando, Pouya Hashemi | 2018-08-14 |
| 10043878 | Vertical field-effect-transistors having multiple threshold voltages | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-08-07 |
| 10043825 | Lateral bipolar junction transistor with multiple base lengths | Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning | 2018-08-07 |
| 10037942 | Low resistance contact structures for trench structures | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2018-07-31 |
| 10038050 | FinFET resistor and method to fabricate same | Praneet Adusumilli, Keith E. Fogel, Oscar van der Straten | 2018-07-31 |
| 10038053 | Methods for removal of selected nanowires in stacked gate all around architecture | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-07-31 |
| 10032721 | Low resistance contact structures for trench structures | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2018-07-24 |
| 10032870 | Low defect III-V semiconductor template on porous silicon | Joel P. de Souza, Keith E. Fogel, Dominic J. Schepis | 2018-07-24 |
| 10020384 | Forming a fin using double trench epitaxy | Veeraraghavan S. Basker, Pouya Hashemi, Shogo Mochizuki | 2018-07-10 |
| 10020398 | Stress induction in 3D device channel using elastic relaxation of high stress material | Kangguo Cheng, Nicolas Loubet, Xin Miao | 2018-07-10 |
| 10011920 | Low-temperature selective epitaxial growth of silicon for device integration | Bahman Hekmatshoar-Tabari, Ali Khakifirooz, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi | 2018-07-03 |
| 10014371 | Stressed nanowire stack for field effect transistor | Martin M. Frank, Pouya Hashemi, Ali Khakifirooz | 2018-07-03 |
| 10014322 | Local SOI fins with multiple heights | Kangguo Cheng, Joel P. de Souza, Ali Khakifirooz, Dominic J. Schepis | 2018-07-03 |
| 10008563 | Dielectric with air gaps for use in semiconductor devices | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2018-06-26 |
| 10008596 | Channel-last replacement metal-gate vertical field effect transistor | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-06-26 |
| 10008507 | Metal FinFET anti-fuse | Praneet Adusumilli, Oscar van der Straten, Miaomiao Wang, Chih-Chao Yang | 2018-06-26 |
| 10002948 | FinFET having highly doped source and drain regions | Kangguo Cheng, Ali Khakifirooz, Dominic J. Schepis | 2018-06-19 |
| 10002926 | Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy | Kangguo Cheng, Pouya Hashemi | 2018-06-19 |
| 10002794 | Multiple gate length vertical field-effect-transistors | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-06-19 |
| 10002798 | Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step | Pranita Kerber, Qiqing C. Ouyang, Dominic J. Schepis | 2018-06-19 |
| 10002924 | Devices including high percentage SiGe fins formed at a tight pitch and methods of manufacturing same | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-06-19 |
| 10002789 | High performance middle of line interconnects | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2018-06-19 |