Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
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Alexander Reznicek

IBM: 163 patents #2 of 10,623Top 1%
Globalfoundries: 8 patents #30 of 961Top 4%
Troy, NY: #1 of 59 inventorsTop 2%
New York: #2 of 11,825 inventorsTop 1%
Overall (2018): #6 of 503,207Top 1%
171 Patents 2018

Issued Patents 2018

Showing 151–171 of 171 patents

Patent #TitleCo-InventorsDate
9881798 Metal cap integration by local alloying Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang 2018-01-30
9875939 Methods of forming uniform and pitch independent fin recess Yue Ke, Benjamin G. Moser, Dominic J. Schepis, Melissa A. Smith, Henry K. Utomo +2 more 2018-01-23
9876075 Method of forming dielectric with air gaps for use in semiconductor devices Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang 2018-01-23
9876015 Tight pitch inverter using vertical transistors Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi 2018-01-23
9875896 Method for forming a strained semiconductor layer including replacing an etchable material formed under the strained semiconductor layer with a dielectric layer Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi 2018-01-23
9871140 Dual strained nanosheet CMOS and methods for fabricating Karthik Balakrishnan, Michael A. Guillorn, Pouya Hashemi 2018-01-16
9870953 System on chip material co-integration Takashi Ando, Lukas Czornomaz, Pouya Hashemi 2018-01-16
9865511 Formation of strained fins in a finFET device Pouya Hashemi, Ali Khakifirooz 2018-01-09
9865737 Formation of FinFET junction Kevin K. Chan, Pouya Hashemi, Ali Khakifirooz, John A. Ott 2018-01-09
9865714 III-V lateral bipolar junction transistor Pouya Hashemi, Tak H. Ning 2018-01-09
9865587 Method and structure for forming buried ESD with FinFETs Kangguo Cheng, Nicolas Loubet, Xin Miao 2018-01-09
9865538 Metallic blocking layer for reliable interconnects and contacts Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang 2018-01-09
9865462 Strain relaxed buffer layers with virtually defect free regions Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi 2018-01-09
9859301 Methods for forming hybrid vertical transistors Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi 2018-01-02
9859425 Field-effect transistor with aggressively strained fins Pouya Hashemi, Ali Khakifirooz 2018-01-02
9859420 Tapered vertical FET having III-V channel Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi 2018-01-02
9859371 Semiconductor device including a strain relief buffer Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi 2018-01-02
9859369 Semiconductor device including nanowire transistors with hybrid channels Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz 2018-01-02
9859216 Voidless contact metal structures Veeraraghavan S. Basker, Nicolas L. Breil, Oleg Gluschenkov, Shogo Mochizuki 2018-01-02
9859367 Stacked strained and strain-relaxed hexagonal nanowires Takashi Ando, Pouya Hashemi, John A. Ott 2018-01-02
9859219 Copper wiring structures with copper titanium encapsulation Praneet Adusumilli, Oscar van der Straten 2018-01-02