Issued Patents 2017
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9842767 | Method of forming an interconnection | Ming-Han Lee, Tz-Jun Kuo, Chien-Hsin Ho | 2017-12-12 |
| 9837310 | Method of manufacturing a semiconductor device | Chao-Hsien Peng, Chi-Liang Kuo, Shau-Lin Shue | 2017-12-05 |
| 9818644 | Interconnect structure and manufacturing method thereof | Shin-Yi Yang, Hsi-Wen Tien, Ming-Han Lee, Shau-Lin Shue | 2017-11-14 |
| 9773676 | Lithography using high selectivity spacers for pitch reduction | Yu-Sheng Chang, Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Ming-Feng Shieh +5 more | 2017-09-26 |
| 9728503 | Via pre-fill on back-end-of-the-line interconnect layer | Chao-Hsien Peng, Chi-Liang Kuo, Ming-Han Lee, Shau-Lin Shue | 2017-08-08 |
| 9646932 | Method for forming interconnect structure that avoids via recess | Chao-Hsien Peng, Tsung-Min Huang, Shau-Lin Shue | 2017-05-09 |
| 9640431 | Method for via plating with seed layer | Shin-Yi Yang, Ching-Fu Yeh, Tz-Jun Kuo, Ming-Han Lee | 2017-05-02 |
| 9633949 | Copper etching integration scheme | Chih Wei Lu, Chung-Ju Lee, Tien-I Bao | 2017-04-25 |
| 9613854 | Method and apparatus for back end of line semiconductor device processing | Shin-Yi Yang, Ming-Han Lee, Ching-Fu Yeh, Pei-Yin Liou | 2017-04-04 |
| 9607891 | Aluminum interconnection apparatus | Ching-Fu Yeh | 2017-03-28 |
| 9595471 | Conductive element structure and method | Tai-I Yang, Hsiang-Wei Liu, Chia-Tien Wu, Tien-Lu Lin | 2017-03-14 |
| 9570347 | Method of semiconductor integrated circuit fabrication | Ching-Fu Yeh, Chao-Hsien Peng, Hsien-Chang Wu | 2017-02-14 |
| 9548241 | Semiconductor device metallization systems and methods | Shau-Lin Shue, Keith Kuang-Kuo Koai, Hai-Ching Chen, Tung-Ching Tseng, Wen-Cheng Yang +3 more | 2017-01-17 |