Issued Patents 2017
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9818644 | Interconnect structure and manufacturing method thereof | Hsi-Wen Tien, Ming-Han Lee, Hsiang-Huan Lee, Shau-Lin Shue | 2017-11-14 |
| 9640431 | Method for via plating with seed layer | Ching-Fu Yeh, Tz-Jun Kuo, Hsiang-Huan Lee, Ming-Han Lee | 2017-05-02 |
| 9613854 | Method and apparatus for back end of line semiconductor device processing | Hsiang-Huan Lee, Ming-Han Lee, Ching-Fu Yeh, Pei-Yin Liou | 2017-04-04 |
| 9613856 | Method of forming metal interconnection | Ming-Han Lee, Shau-Lin Shue, Tz-Jun Kuo | 2017-04-04 |