Issued Patents 2017
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9837310 | Method of manufacturing a semiconductor device | Chao-Hsien Peng, Chi-Liang Kuo, Hsiang-Huan Lee | 2017-12-05 |
| 9831117 | Self-aligned double spacer patterning process | Yung-Hsu Wu, Tsung-Min Huang, Cheng-Hsiung Tsai, Chung-Ju Lee, Tien-I Bao | 2017-11-28 |
| 9818644 | Interconnect structure and manufacturing method thereof | Shin-Yi Yang, Hsi-Wen Tien, Ming-Han Lee, Hsiang-Huan Lee | 2017-11-14 |
| 9799558 | Method for forming conductive structure in semiconductor structure | Hsi-Wen Tien, Carlos H. Diaz, Chung-Ju Lee, Tien-I Bao | 2017-10-24 |
| 9773676 | Lithography using high selectivity spacers for pitch reduction | Yu-Sheng Chang, Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Hsiang-Huan Lee +5 more | 2017-09-26 |
| 9741567 | Method of forming multiple patterning spacer structures | Chih Wei Lu, Chung-Ju Lee | 2017-08-22 |
| 9735052 | Metal lines for interconnect structure and method of manufacturing same | Cheng-Hsiung Tsai, Carlos H. Diaz, Chung-Ju Lee, Tien-I Bao, Yung-Hsu Wu +1 more | 2017-08-15 |
| 9728503 | Via pre-fill on back-end-of-the-line interconnect layer | Chao-Hsien Peng, Chi-Liang Kuo, Ming-Han Lee, Hsiang-Huan Lee | 2017-08-08 |
| 9728485 | Semiconductor device with interconnect structure having catalys layer | Ming-Han Lee | 2017-08-08 |
| 9721894 | Semiconductor device and manufacturing method thereof | Shih-Kang Fu, Hsien-Chang Wu, Li-Lin Su, Ming-Han Lee | 2017-08-01 |
| 9721887 | Method of forming metal interconnection | Chao-Hsien Peng, Chih Wei Lu, Ming-Han Lee | 2017-08-01 |
| 9716074 | Wafer backside interconnect structure connected to TSVs | Ming-Fa Chen, Wen-Chih Chiou | 2017-07-25 |
| 9704806 | Additional etching to increase via contact area | Pei-Yi Lin, Chung-Ju Lee | 2017-07-11 |
| 9685368 | Interconnect structure having an etch stop layer over conductive lines | Cheng-Hsiung Tsai, Chung-Ju Lee, Tien-I Bao | 2017-06-20 |
| 9659864 | Method and apparatus for forming self-aligned via with selectively deposited etching stop layer | Yung-Hsu Wu, Hai-Ching Chen, Jung-Hsun Tsai, Tien-I Bao | 2017-05-23 |
| 9653349 | Semiconductor integrated circuit with nano gap | Cheng-Hsiung Tsai, Chieh-Han Wu, Chung-Ju Lee | 2017-05-16 |
| 9646932 | Method for forming interconnect structure that avoids via recess | Chao-Hsien Peng, Tsung-Min Huang, Hsiang-Huan Lee | 2017-05-09 |
| 9627206 | Method of double patterning lithography process using plurality of mandrels for integrated circuit applications | Chung-Ju Lee, Hsin-Chieh Yao, Tien-I Bao, Yung-Hsu Wu | 2017-04-18 |
| 9613856 | Method of forming metal interconnection | Shin-Yi Yang, Ming-Han Lee, Tz-Jun Kuo | 2017-04-04 |
| 9607850 | Self-aligned double spacer patterning process | Cheng-Hsiung Tsai, Yung-Hsu Wu, Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao | 2017-03-28 |
| 9589890 | Method for interconnect scheme | Hsin-Chieh Yao, Carlos H. Diaz, Cheng-Hsiung Tsai, Chung-Ju Lee, Chien-Hua Huang +3 more | 2017-03-07 |
| 9576814 | Method of spacer patterning to form a target integrated circuit pattern | Chieh-Han Wu, Cheng-Hsiung Tsai, Chung-Ju Lee, Ming-Feng Shieh, Ru-Gun Liu +1 more | 2017-02-21 |
| 9564397 | Interconnect structure and method of forming the same | Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Tien-I Bao | 2017-02-07 |
| 9548241 | Semiconductor device metallization systems and methods | Hsiang-Huan Lee, Keith Kuang-Kuo Koai, Hai-Ching Chen, Tung-Ching Tseng, Wen-Cheng Yang +3 more | 2017-01-17 |