Issued Patents 2017
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9852915 | Etching apparatus | Wan-Yu Lee, Ying-Hao Kuo, Hai-Ching Chen | 2017-12-26 |
| 9831117 | Self-aligned double spacer patterning process | Yung-Hsu Wu, Tsung-Min Huang, Cheng-Hsiung Tsai, Chung-Ju Lee, Shau-Lin Shue | 2017-11-28 |
| 9831090 | Method and structure for semiconductor device having gate spacer protection layer | Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Chien-Hua Huang | 2017-11-28 |
| 9818690 | Self-aligned interconnection structure and method | Jung-Hsun Tsai, Chi-Lin Teng, Kai-Fang Cheng, Hsin-Yen Huang, Hai-Ching Chen +1 more | 2017-11-14 |
| 9806026 | Self repairing process for porous dielectric materials | Tsung-Min Huang, Chung-Ju Lee | 2017-10-31 |
| 9799558 | Method for forming conductive structure in semiconductor structure | Hsi-Wen Tien, Carlos H. Diaz, Chung-Ju Lee, Shau-Lin Shue | 2017-10-24 |
| 9799603 | Semiconductor device structure and method for forming the same | Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Chen, Hsin-Yen Huang, Jung-Hsun Tsai | 2017-10-24 |
| 9793264 | Vertical metal insulator metal capacitor having a high-K dielectric material | Chewn-Pu Jou | 2017-10-17 |
| 9786549 | Etch damage and ESL free dual damascene metal interconnect | Sunil Kumar Singh, Chung-Ju Lee | 2017-10-10 |
| 9773676 | Lithography using high selectivity spacers for pitch reduction | Yu-Sheng Chang, Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Hsiang-Huan Lee +5 more | 2017-09-26 |
| 9768024 | Multi-layer mask and method of forming same | Teng-Chun Tsai, Yung-Cheng Lu, Ying-Tsung Chen | 2017-09-19 |
| 9735052 | Metal lines for interconnect structure and method of manufacturing same | Cheng-Hsiung Tsai, Carlos H. Diaz, Chung-Ju Lee, Shau-Lin Shue, Yung-Hsu Wu +1 more | 2017-08-15 |
| 9709905 | System and method for dark field inspection | Bo-Jiun Lin, Hai-Ching Chen, Hsin-Chieh Yao | 2017-07-18 |
| 9698100 | Structure and method for interconnection | Chih Wei Lu, Chung-Ju Lee | 2017-07-04 |
| 9685368 | Interconnect structure having an etch stop layer over conductive lines | Cheng-Hsiung Tsai, Chung-Ju Lee, Shau-Lin Shue | 2017-06-20 |
| 9659857 | Semiconductor structure and method making the same | Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Cheng | 2017-05-23 |
| 9659864 | Method and apparatus for forming self-aligned via with selectively deposited etching stop layer | Yung-Hsu Wu, Hai-Ching Chen, Jung-Hsun Tsai, Shau-Lin Shue | 2017-05-23 |
| 9651736 | Self-alignment due to wettability difference of an interface | Jay Lai, Ying-Hao Kuo, Hai-Ching Chen | 2017-05-16 |
| 9640397 | Method of fabricating a semiconductor integrated circuit using a directed self-assembly block copolymer | Chieh-Han Wu, Chung-Ju Lee, Tsung-Yu Chen, Shinn-Sheng Yu, Yu-Fu Lin +1 more | 2017-05-02 |
| 9633958 | Bonding pad surface damage reduction in a formation of digital pattern generator | Chih Wei Lu, Tsung-Chih Chien, Hui-Min Huang | 2017-04-25 |
| 9633949 | Copper etching integration scheme | Chih Wei Lu, Chung-Ju Lee, Hsiang-Huan Lee | 2017-04-25 |
| 9627206 | Method of double patterning lithography process using plurality of mandrels for integrated circuit applications | Chung-Ju Lee, Hsin-Chieh Yao, Shau-Lin Shue, Yung-Hsu Wu | 2017-04-18 |
| 9614053 | Spacers with rectangular profile and methods of forming the same | Yu-Sheng Chang, Chung-Ju Lee | 2017-04-04 |
| 9607850 | Self-aligned double spacer patterning process | Cheng-Hsiung Tsai, Yung-Hsu Wu, Tsung-Min Huang, Chung-Ju Lee, Shau-Lin Shue | 2017-03-28 |
| 9589890 | Method for interconnect scheme | Hsin-Chieh Yao, Carlos H. Diaz, Cheng-Hsiung Tsai, Chung-Ju Lee, Chien-Hua Huang +3 more | 2017-03-07 |