Issued Patents 2017
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9831090 | Method and structure for semiconductor device having gate spacer protection layer | Chih Wei Lu, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao | 2017-11-28 |
| 9831117 | Self-aligned double spacer patterning process | Yung-Hsu Wu, Tsung-Min Huang, Cheng-Hsiung Tsai, Tien-I Bao, Shau-Lin Shue | 2017-11-28 |
| 9818695 | Material and process for copper barrier layer | Tsung-Min Huang | 2017-11-14 |
| 9806026 | Self repairing process for porous dielectric materials | Tsung-Min Huang, Tien-I Bao | 2017-10-31 |
| 9799558 | Method for forming conductive structure in semiconductor structure | Hsi-Wen Tien, Carlos H. Diaz, Shau-Lin Shue, Tien-I Bao | 2017-10-24 |
| 9786549 | Etch damage and ESL free dual damascene metal interconnect | Sunil Kumar Singh, Tien-I Bao | 2017-10-10 |
| 9773676 | Lithography using high selectivity spacers for pitch reduction | Yu-Sheng Chang, Cheng-Hsiung Tsai, Hai-Ching Chen, Hsiang-Huan Lee, Ming-Feng Shieh +5 more | 2017-09-26 |
| 9768031 | Semiconductor device manufacturing methods | Tsung-Min Huang, Cheng-Hsiung Tsai | 2017-09-19 |
| 9741567 | Method of forming multiple patterning spacer structures | Chih Wei Lu, Shau-Lin Shue | 2017-08-22 |
| 9735048 | Semiconductor device and fabricating process for the same | Chien-Hua Huang, Tsung-Min Huang | 2017-08-15 |
| 9735052 | Metal lines for interconnect structure and method of manufacturing same | Cheng-Hsiung Tsai, Carlos H. Diaz, Shau-Lin Shue, Tien-I Bao, Yung-Hsu Wu +1 more | 2017-08-15 |
| 9728408 | Method of semiconductor integrated circuit fabrication | Chih-Tsung Shih, Jeng-Horng Chen, Shinn-Sheng Yu, Tsung-Min Huang, Anthony Yen | 2017-08-08 |
| 9704806 | Additional etching to increase via contact area | Pei-Yi Lin, Shau-Lin Shue | 2017-07-11 |
| 9698100 | Structure and method for interconnection | Chih Wei Lu, Tien-I Bao | 2017-07-04 |
| 9685368 | Interconnect structure having an etch stop layer over conductive lines | Cheng-Hsiung Tsai, Shau-Lin Shue, Tien-I Bao | 2017-06-20 |
| 9679803 | Method for forming different patterns in a semiconductor structure using a single mask | Tsung-Min Huang, Chih-Tsung Shih, Yen-Cheng Lu | 2017-06-13 |
| 9653349 | Semiconductor integrated circuit with nano gap | Cheng-Hsiung Tsai, Chieh-Han Wu, Shau-Lin Shue | 2017-05-16 |
| 9640397 | Method of fabricating a semiconductor integrated circuit using a directed self-assembly block copolymer | Chieh-Han Wu, Tien-I Bao, Tsung-Yu Chen, Shinn-Sheng Yu, Yu-Fu Lin +1 more | 2017-05-02 |
| 9633999 | Method and structure for semiconductor mid-end-of-line (MEOL) process | Chih Wei Lu, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen | 2017-04-25 |
| 9633949 | Copper etching integration scheme | Chih Wei Lu, Hsiang-Huan Lee, Tien-I Bao | 2017-04-25 |
| 9627206 | Method of double patterning lithography process using plurality of mandrels for integrated circuit applications | Hsin-Chieh Yao, Shau-Lin Shue, Tien-I Bao, Yung-Hsu Wu | 2017-04-18 |
| 9627256 | Integrated circuit interconnects and methods of making same | Cheng-Hsiung Tsai, Bo-Jiun Lin, Hsien-Chang Wu | 2017-04-18 |
| 9627215 | Structure and method for interconnection | Chien-Hua Huang, Cheng-Hsiung Tsai, Cherng-Shiaw Tsai | 2017-04-18 |
| 9614053 | Spacers with rectangular profile and methods of forming the same | Yu-Sheng Chang, Tien-I Bao | 2017-04-04 |
| 9607850 | Self-aligned double spacer patterning process | Cheng-Hsiung Tsai, Yung-Hsu Wu, Tsung-Min Huang, Tien-I Bao, Shau-Lin Shue | 2017-03-28 |