Issued Patents 2017
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9831117 | Self-aligned double spacer patterning process | Tsung-Min Huang, Cheng-Hsiung Tsai, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue | 2017-11-28 |
| 9773676 | Lithography using high selectivity spacers for pitch reduction | Yu-Sheng Chang, Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Hsiang-Huan Lee +5 more | 2017-09-26 |
| 9735052 | Metal lines for interconnect structure and method of manufacturing same | Cheng-Hsiung Tsai, Carlos H. Diaz, Chung-Ju Lee, Shau-Lin Shue, Tien-I Bao +1 more | 2017-08-15 |
| 9659864 | Method and apparatus for forming self-aligned via with selectively deposited etching stop layer | Hai-Ching Chen, Jung-Hsun Tsai, Shau-Lin Shue, Tien-I Bao | 2017-05-23 |
| 9627206 | Method of double patterning lithography process using plurality of mandrels for integrated circuit applications | Chung-Ju Lee, Hsin-Chieh Yao, Shau-Lin Shue, Tien-I Bao | 2017-04-18 |
| 9607850 | Self-aligned double spacer patterning process | Cheng-Hsiung Tsai, Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue | 2017-03-28 |
| 9601346 | Spacer-damage-free etching | Tsung-Min Huang, Chung-Ju Lee | 2017-03-21 |
| 9589890 | Method for interconnect scheme | Hsin-Chieh Yao, Carlos H. Diaz, Cheng-Hsiung Tsai, Chung-Ju Lee, Chien-Hua Huang +3 more | 2017-03-07 |
| 9576896 | Semiconductor arrangement and formation thereof | Yu-Chieh Liao, Cheng-Chi Chuang, Tai-I Yang, Tien-Lu Lin | 2017-02-21 |