Issued Patents 2017
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9837354 | Hybrid copper structure for advance interconnect usage | Hsiang-Wei Liu, Cheng-Chi Chuang, Tien-Lu Lin | 2017-12-05 |
| 9805970 | Method for forming deep trench spacing isolation for CMOS image sensors | Jung-I Lin, Ta-Chun Lin, Tien-Lu Lin, Chen-Jong Wang | 2017-10-31 |
| 9735232 | Method for manufacturing a semiconductor structure having a trench with high aspect ratio | Jheng-Sheng YOU, Chi-Fu Lin, Tien-Lu Lin | 2017-08-15 |
| 9716035 | Combination interconnect structure and methods of forming same | Yung-Chih Wang, Cheng-Chi Chuang, Chia-Tien Wu, Tien-Lu Lin | 2017-07-25 |
| 9698242 | Semiconductor arrangement and formation thereof | Tien-Lu Lin, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu | 2017-07-04 |
| 9633897 | Air-gap forming techniques for interconnect structures | Cheng-Chi Chuang, Yung-Chih Wang, Tien-Lu Lin | 2017-04-25 |
| 9614031 | Methods for forming a high-voltage super junction by trench and epitaxial doping | Shou-Wei Lee, Shao-Chi Yu, Hong-Seng Shue, Kun-Ming Huang, Po-Tao Chu | 2017-04-04 |
| 9595471 | Conductive element structure and method | Hsiang-Wei Liu, Chia-Tien Wu, Hsiang-Huan Lee, Tien-Lu Lin | 2017-03-14 |
| 9583434 | Metal line structure and method | Hsiang-Lun Kao, Hsiang-Wei Liu, Jian-Hua Chen, Yu-Chieh Liao, Yung-Chih Wang +1 more | 2017-02-28 |
| 9576896 | Semiconductor arrangement and formation thereof | Yu-Chieh Liao, Cheng-Chi Chuang, Tien-Lu Lin, Yung-Hsu Wu | 2017-02-21 |
| 9558986 | Semiconductor structure and manufacturing method thereof | Hong-Seng Shue, Kun-Ming Huang, Chih-Heng Shen, Po-Tao Chu | 2017-01-31 |
| 9559134 | Deep trench spacing isolation for complementary metal-oxide-semiconductor (CMOS) image sensors | Jung-I Lin, Ta-Chun Lin, Tien-Lu Lin, Chen-Jong Wang | 2017-01-31 |