Issued Patents 2017
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9852908 | Methods for integrated circuit design and fabrication | Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai +1 more | 2017-12-26 |
| 9823066 | Method for validating measurement data | Chui-Jung Chiu, Jen-Chieh Lo, Ying-Chou Cheng | 2017-11-21 |
| 9799529 | Method of planarizing a film layer | Yung-Sung Yen, Wei-Liang Lin, Hsin-Chih Chen | 2017-10-24 |
| 9793211 | Dual power structure with connection pins | Shih-Wei Peng, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young +3 more | 2017-10-17 |
| 9773676 | Lithography using high selectivity spacers for pitch reduction | Yu-Sheng Chang, Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Hsiang-Huan Lee +5 more | 2017-09-26 |
| 9761436 | Mechanisms for forming patterns using multiple lithography processes | Shih-Ming Chang, Ming-Feng Shieh, Chih-Ming Lai, Tsai-Sheng Gau | 2017-09-12 |
| 9754073 | Layout optimization for integrated circuit design | Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Lee-Chung Lu | 2017-09-05 |
| 9754881 | Designed-based interconnect structure in semiconductor structure | Chih-Liang Chen, Chih-Ming Lai, Yung-Sung Yen, Kam-Tou Sio, Tsong-Hua Ou +3 more | 2017-09-05 |
| 9747408 | Generating final mask pattern by performing inverse beam technology process | Hsu-Ting Huang, Shuo-Yen Chou, Tsai-Sheng Gau | 2017-08-29 |
| 9735140 | Systems and methods for a sequential spacer scheme | Shih-Ming Chang, Ming-Feng Shieh, Tsai-Sheng Gau | 2017-08-15 |
| 9728407 | Method of forming features with various dimensions | Ken-Hsien Hsieh, Chi-Cheng Hung, Chih-Ming Lai, Wei-Liang Lin, Chun-Kuang Chen | 2017-08-08 |
| 9716032 | Via-free interconnect structure with self-aligned metal line interconnections | Yu-Po Tang, Shih-Ming Chang, Ken-Hsien Hsieh | 2017-07-25 |
| 9684236 | Method of patterning a film layer | Ken-Hsien Hsieh, Kuan-Hsin Lo, Shih-Ming Chang, Wei-Liang Lin, Joy Cheng +5 more | 2017-06-20 |
| 9679994 | High fin cut fabrication process | L. C. Chou, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng +3 more | 2017-06-13 |
| 9679100 | Environmental-surrounding-aware OPC | Wen-Li Cheng, Ming-Hui Chih, Wen-Chun Huang | 2017-06-13 |
| 9627310 | Semiconductor device with self-aligned interconnects | Shih-Ming Chang, Ken-Hsien Hsieh, Tsong-Hua Ou, Fang-Yu Fan, Yuan-Te Hou | 2017-04-18 |
| 9627262 | Method of patterning features of a semiconductor device | Wei-Chao Chiu, Chen Chen, Chih-Ming Lai, Ming-Feng Shieh, Nian-Fuh Cheng +1 more | 2017-04-18 |
| 9612526 | Photomask and method for fabricating integrated circuit | Chun Lin, Yi-Jie Chen, Feng-Yuan Chiu, Ying-Chou Cheng, Kuei-Liang Lu +2 more | 2017-04-04 |
| 9613850 | Lithographic technique for feature cut by line-end shrink | Yung-Sung Yen, Chun-Kuang Chen, Ko-Bin Kao, Ken-Hsien Hsieh | 2017-04-04 |
| 9594866 | Method for checking and fixing double-patterning layout | Dio Wang, Ken-Hsien Hsieh, Huang-Yu Chen, Li-Chun Tien, Lee-Chung Lu | 2017-03-14 |
| 9581900 | Self aligned patterning with multiple resist layers | Ming-Feng Shieh, Chih-Ming Lai, Ken-Hsien Hsieh, Shih-Ming Chang | 2017-02-28 |
| 9576814 | Method of spacer patterning to form a target integrated circuit pattern | Chieh-Han Wu, Cheng-Hsiung Tsai, Chung-Ju Lee, Ming-Feng Shieh, Shau-Lin Shue +1 more | 2017-02-21 |
| 9564327 | Method for forming line end space structure using trimmed photo resist | Chia-Ying Lee, Jyu-Horng Shieh, Ming-Feng Shieh, Shih-Ming Chang, Chih-Ming Lai +1 more | 2017-02-07 |