Issued Patents 2017
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9754073 | Layout optimization for integrated circuit design | Huang-Yu Chen, Yuan-Te Hou, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu | 2017-09-05 |
| 9553043 | Interconnect structure having smaller transition layer via | Lee-Chung Lu, Wen-Hao Chen, Yuan-Te Hou, Fang-Yu Fan, Dian-Hau Chen +2 more | 2017-01-24 |