Issued Patents 2017
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9754073 | Layout optimization for integrated circuit design | Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu | 2017-09-05 |
| 9747402 | Methods for double-patterning-compliant standard cell design | Yuan-Te Hou, Fung Song Lee, Wen-Ju Yang, Gwan Sin Chang, Yi-Kan Cheng +2 more | 2017-08-29 |
| 9640450 | Method for reducing light-induced-degradation in manufacturing solar cell | Kuang-Yang Kuo, Wei-Lun LU, Chien-Chun Wang, Yu-Pan Pai | 2017-05-02 |
| 9594866 | Method for checking and fixing double-patterning layout | Dio Wang, Ken-Hsien Hsieh, Li-Chun Tien, Ru-Gun Liu, Lee-Chung Lu | 2017-03-14 |