Issued Patents 2017
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9853008 | Connecting techniques for stacked CMOS devices | Hsiang-Jen Tseng, Wei-Yu Chen, Ting-Wei Chiang | 2017-12-26 |
| 9846757 | Cell grid architecture for FinFET technology | Hui-Zhong Zhuang, Ting-Wei Chiang, Chung-Te Lin | 2017-12-19 |
| 9846755 | Method for cell placement in semiconductor layout and system thereof | Ming-Zhang Kuo, Lee-Chung Lu, Cheng-Chung Lin, Sang Hoo Dhong, Ta-Pen Guo | 2017-12-19 |
| 9831230 | Standard cell layout, semiconductor device having engineering change order (ECO) cells and method | Ya-Chi Chou, Hui-Zhong Zhuang, Chun-Fu Chen, Ting-Wei Chiang, Hsiang-Jen Tseng | 2017-11-28 |
| 9806071 | Integrated circuit with elongated coupling | Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Ting-Wei Chiang, Sheng-Hsiung Wang | 2017-10-31 |
| 9767243 | System and method of layout design for integrated circuits | Ting-Wei Chiang, Hui-Zhong Zhuang | 2017-09-19 |
| 9747402 | Methods for double-patterning-compliant standard cell design | Huang-Yu Chen, Yuan-Te Hou, Fung Song Lee, Wen-Ju Yang, Gwan Sin Chang +2 more | 2017-08-29 |
| 9691666 | Layout architecture for performance improvement | Lee-Chung Lu, Hui-Zhong Zhuang | 2017-06-27 |
| 9690892 | Masks based on gate pad layout patterns of standard cell having different gate pad pitches | Ting-Wei Chiang, Shun Li Chen, Yi-Hsun Chiu | 2017-06-27 |
| 9691750 | Semiconductor device and layout method thereof | Ting Wei Chou, WEN-LANG WU, Chitong Chen, Shun Li Chen, Ting-Wei Chiang | 2017-06-27 |
| 9653393 | Method and layout of an integrated circuit | Wei-Yu Chen, Hui-Zhong Zhuang, Ting-Wei Chiang, Hsiang-Jen Tseng | 2017-05-16 |
| 9626472 | Method and system of forming layout design | Ting-Wei Chiang, Hui-Zhong Zhuang, Zhe-Wei Jiang | 2017-04-18 |
| 9608604 | Voltage level shifter with single well voltage | Lee-Chung Lu, Chung-Hsing Wang, Chun-Hui Tai, Shun Li Chen | 2017-03-28 |
| 9594866 | Method for checking and fixing double-patterning layout | Dio Wang, Ken-Hsien Hsieh, Huang-Yu Chen, Ru-Gun Liu, Lee-Chung Lu | 2017-03-14 |
| 9563731 | Cell boundaries for self aligned multiple patterning abutments | Chin-Hsiung Hsu, Pin-Dai Sue, Ching-Hsiang Chang, Wen-Hao Chen, Cheng-I Huang | 2017-02-07 |
| 9543193 | Non-hierarchical metal layers for integrated circuits | Lee-Chung Lu, Yuan-Te Hou, Shyue-Shyh Lin, Dian-Hau Chen | 2017-01-10 |
| 9536032 | Method and system of layout placement based on multilayer gridlines | Ting-Wei Chiang, Hui-Zhong Zhuang, Zhe-Wei Jiang | 2017-01-03 |