TC

Ting-Wei Chiang

TSMC: 13 patents #102 of 2,832Top 4%
Overall (2017): #3,824 of 506,227Top 1%
13
Patents 2017

Issued Patents 2017

Showing 1–13 of 13 patents

Patent #TitleCo-InventorsDate
9853008 Connecting techniques for stacked CMOS devices Hsiang-Jen Tseng, Wei-Yu Chen, Li-Chun Tien 2017-12-26
9846759 Global connection routing method and system for performing the same Sheng-Hsiung Chen, Jyun-Hao Chang, Fong-Yuan Chang, I-Lun Tseng, Po-Hsiang Huang 2017-12-19
9846757 Cell grid architecture for FinFET technology Hui-Zhong Zhuang, Chung-Te Lin, Li-Chun Tien 2017-12-19
9831230 Standard cell layout, semiconductor device having engineering change order (ECO) cells and method Li-Chun Tien, Ya-Chi Chou, Hui-Zhong Zhuang, Chun-Fu Chen, Hsiang-Jen Tseng 2017-11-28
9806071 Integrated circuit with elongated coupling Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Li-Chun Tien 2017-10-31
9767243 System and method of layout design for integrated circuits Hui-Zhong Zhuang, Li-Chun Tien 2017-09-19
9691750 Semiconductor device and layout method thereof Ting Wei Chou, WEN-LANG WU, Chitong Chen, Shun Li Chen, Li-Chun Tien 2017-06-27
9690892 Masks based on gate pad layout patterns of standard cell having different gate pad pitches Shun Li Chen, Yi-Hsun Chiu, Li-Chun Tien 2017-06-27
9659129 Standard cell having cell height being non-integral multiple of nominal minimum pitch Shang-Chih Hsieh, Hui-Zhong Zhuang, Chun-Fu Chen, Hsiang-Jen Tseng 2017-05-23
9653393 Method and layout of an integrated circuit Wei-Yu Chen, Li-Chun Tien, Hui-Zhong Zhuang, Hsiang-Jen Tseng 2017-05-16
9641161 Flip-flop with delineated layout for reduced footprint Chi-Lin Liu, Jerry Chang Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Shang-Chih Hsieh +1 more 2017-05-02
9626472 Method and system of forming layout design Li-Chun Tien, Hui-Zhong Zhuang, Zhe-Wei Jiang 2017-04-18
9536032 Method and system of layout placement based on multilayer gridlines Li-Chun Tien, Hui-Zhong Zhuang, Zhe-Wei Jiang 2017-01-03