Issued Patents 2017
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9853008 | Connecting techniques for stacked CMOS devices | Wei-Yu Chen, Ting-Wei Chiang, Li-Chun Tien | 2017-12-26 |
| 9831230 | Standard cell layout, semiconductor device having engineering change order (ECO) cells and method | Li-Chun Tien, Ya-Chi Chou, Hui-Zhong Zhuang, Chun-Fu Chen, Ting-Wei Chiang | 2017-11-28 |
| 9659129 | Standard cell having cell height being non-integral multiple of nominal minimum pitch | Shang-Chih Hsieh, Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen | 2017-05-23 |
| 9653393 | Method and layout of an integrated circuit | Wei-Yu Chen, Li-Chun Tien, Hui-Zhong Zhuang, Ting-Wei Chiang | 2017-05-16 |