Issued Patents 2017
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9846757 | Cell grid architecture for FinFET technology | Ting-Wei Chiang, Chung-Te Lin, Li-Chun Tien | 2017-12-19 |
| 9831230 | Standard cell layout, semiconductor device having engineering change order (ECO) cells and method | Li-Chun Tien, Ya-Chi Chou, Chun-Fu Chen, Ting-Wei Chiang, Hsiang-Jen Tseng | 2017-11-28 |
| 9806071 | Integrated circuit with elongated coupling | Tung-Heng Hsieh, Chung-Te Lin, Ting-Wei Chiang, Sheng-Hsiung Wang, Li-Chun Tien | 2017-10-31 |
| 9767243 | System and method of layout design for integrated circuits | Ting-Wei Chiang, Li-Chun Tien | 2017-09-19 |
| 9691666 | Layout architecture for performance improvement | Lee-Chung Lu, Li-Chun Tien | 2017-06-27 |
| 9679915 | Integrated circuit with well and substrate contacts | Ming-Zhang Kuo, Ho-Chieh Hsieh, Kuo-Feng TSENG, Lee-Chung Lu, Cheng-Chung Lin +1 more | 2017-06-13 |
| 9659129 | Standard cell having cell height being non-integral multiple of nominal minimum pitch | Shang-Chih Hsieh, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng | 2017-05-23 |
| 9653393 | Method and layout of an integrated circuit | Wei-Yu Chen, Li-Chun Tien, Ting-Wei Chiang, Hsiang-Jen Tseng | 2017-05-16 |
| 9641161 | Flip-flop with delineated layout for reduced footprint | Chi-Lin Liu, Ting-Wei Chiang, Jerry Chang Jui Kao, Lee-Chung Lu, Shang-Chih Hsieh +1 more | 2017-05-02 |
| 9626472 | Method and system of forming layout design | Ting-Wei Chiang, Li-Chun Tien, Zhe-Wei Jiang | 2017-04-18 |
| 9536032 | Method and system of layout placement based on multilayer gridlines | Ting-Wei Chiang, Li-Chun Tien, Zhe-Wei Jiang | 2017-01-03 |