Issued Patents 2017
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9852989 | Power grid of integrated circuit | Chin-Shen Lin, Min-Yuan Tsai, Kuo-Nan Yang | 2017-12-26 |
| 9799639 | Power gating for three dimensional integrated circuits (3DIC) | Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang +1 more | 2017-10-24 |
| 9672315 | Optimization for circuit migration | Lee-Chung Lu, Yi-Kan Cheng, Chen-Fu Huang, Hsiao-Shu Chao, Chin-Yu Chiang +3 more | 2017-06-06 |
| 9659133 | Method, system and computer program product for generating layout for semiconductor device | Yen-Hung Lin, Chi Wei Hu, Yuan-Te Hou, Chin-Chou Liu | 2017-05-23 |
| 9608604 | Voltage level shifter with single well voltage | Lee-Chung Lu, Chun-Hui Tai, Li-Chun Tien, Shun Li Chen | 2017-03-28 |
| 9589885 | Device having multiple-layer pins in memory MUX1 layout | Hung-Jen Liao, Jung-Hsuan Chen, Chien-Chi TIEN, Ching-Wei Wu, Jui-Che Tsai +1 more | 2017-03-07 |
| 9563734 | Characterizing cell using input waveform generation considering different circuit topologies | King-Ho Tam, Yen-Pin Chen, Wen-Hao Chen | 2017-02-07 |
| 9564896 | Post-silicon tuning in voltage control of semiconductor integrated circuits | Jerry Chang Jui Kao, Chien-Ju Chao, Chin-Shen Lin, Nitesh Katta, Kuo-Nan Yang | 2017-02-07 |