Issued Patents 2017
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9852908 | Methods for integrated circuit design and fabrication | Tsong-Hua Ou, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu +1 more | 2017-12-26 |
| 9773671 | Material composition and process for mitigating assist feature pattern transfer | Meng CHEN, Chen-Hau Wu, Meng-Wei Chen, Kuei-Shun Chen, Yu-Chin Huang +2 more | 2017-09-26 |
| 9754073 | Layout optimization for integrated circuit design | Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ru-Gun Liu, Lee-Chung Lu | 2017-09-05 |
| 9728407 | Method of forming features with various dimensions | Chi-Cheng Hung, Chih-Ming Lai, Wei-Liang Lin, Chun-Kuang Chen, Ru-Gun Liu | 2017-08-08 |
| 9716032 | Via-free interconnect structure with self-aligned metal line interconnections | Yu-Po Tang, Shih-Ming Chang, Ru-Gun Liu | 2017-07-25 |
| 9684236 | Method of patterning a film layer | Kuan-Hsin Lo, Shih-Ming Chang, Wei-Liang Lin, Joy Cheng, Chun-Kuang Chen +5 more | 2017-06-20 |
| 9627310 | Semiconductor device with self-aligned interconnects | Shih-Ming Chang, Tsong-Hua Ou, Ru-Gun Liu, Fang-Yu Fan, Yuan-Te Hou | 2017-04-18 |
| 9613850 | Lithographic technique for feature cut by line-end shrink | Yung-Sung Yen, Chun-Kuang Chen, Ko-Bin Kao, Ru-Gun Liu | 2017-04-04 |
| 9594866 | Method for checking and fixing double-patterning layout | Dio Wang, Huang-Yu Chen, Li-Chun Tien, Ru-Gun Liu, Lee-Chung Lu | 2017-03-14 |
| 9581900 | Self aligned patterning with multiple resist layers | Ming-Feng Shieh, Chih-Ming Lai, Ru-Gun Liu, Shih-Ming Chang | 2017-02-28 |
| 9564327 | Method for forming line end space structure using trimmed photo resist | Chia-Ying Lee, Jyu-Horng Shieh, Ming-Feng Shieh, Shih-Ming Chang, Chih-Ming Lai +1 more | 2017-02-07 |