Issued Patents 2017
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9846755 | Method for cell placement in semiconductor layout and system thereof | Ming-Zhang Kuo, Lee-Chung Lu, Cheng-Chung Lin, Li-Chun Tien, Sang Hoo Dhong | 2017-12-19 |
| 9825043 | Semiconductor devices and methods of manufacture thereof | Jean-Pierre Colinge, Carlos H. Diaz | 2017-11-21 |
| 9764950 | Semiconductor arrangement with one or more semiconductor columns | Jean-Pierre Colinge, Chih-Hao Wang, Carlos H. Diaz | 2017-09-19 |
| 9735146 | Vertical nanowire transistor for input/output structure | Jean-Pierre Colinge, Carlos H. Diaz | 2017-08-15 |
| 9691695 | Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure | Carlos H. Diaz, Jean-Pierre Colinge, Yi-Hsiung Lin | 2017-06-27 |
| 9673209 | Memory device and method for fabricating the same | Jean-Pierre Colinge, Carlos H. Diaz | 2017-06-06 |
| 9660107 | 3D cross-bar nonvolatile memory | Jean-Pierre Colinge, Carlos H. Diaz | 2017-05-23 |
| 9659632 | SRAM with stacked bit cells | Carlos H. Diaz, Chih-Hao Wang, Jean-Pierre Colinge | 2017-05-23 |
| 9653457 | Stacked device and associated layout structure | Carlos H. Diaz, Chih-Hao Wang, Jean-Pierre Colinge | 2017-05-16 |
| 9640645 | Semiconductor device with silicide | Jean-Pierre Colinge, Kuo-Cheng Ching, Carlos H. Diaz | 2017-05-02 |
| 9620422 | Semiconductor arrangement | Jean-Pierre Colinge, Chung-Cheng Wu, Sang Hoo Dhong | 2017-04-11 |
| 9614091 | Gate structure and method for fabricating the same | Jean-Pierre Colinge, Carlos H. Diaz | 2017-04-04 |