Issued Patents 2017
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9853150 | Method of fabricating epitaxial gate dielectrics and semiconductor device of the same | Ken-Ichi Goto, Zhiqiang Wu | 2017-12-26 |
| 9825043 | Semiconductor devices and methods of manufacture thereof | Carlos H. Diaz, Ta-Pen Guo | 2017-11-21 |
| 9786774 | Metal gate of gate-all-around transistor | Chi-Wen Liu | 2017-10-10 |
| 9779959 | Structure and formation method of semiconductor device structure | Carlos H. Diaz | 2017-10-03 |
| 9773868 | Nanowire MOSFET with support structures for source and drain | Chien-Hsun Wang, Mao-Lin Huang, Chun-Hsiung Lin | 2017-09-26 |
| 9764950 | Semiconductor arrangement with one or more semiconductor columns | Ta-Pen Guo, Chih-Hao Wang, Carlos H. Diaz | 2017-09-19 |
| 9735146 | Vertical nanowire transistor for input/output structure | Ta-Pen Guo, Carlos H. Diaz | 2017-08-15 |
| 9735255 | Method for fabricating a finFET device including a stem region of a fin element | Kuo-Cheng Ching, Zhiqiang Wu | 2017-08-15 |
| 9728602 | Variable channel strain of nanowire transistors to improve drive current | Tsung-Hsing Yu, Yeh Hsu, Chia-Wen Liu | 2017-08-08 |
| 9698270 | FinFET with dual workfunction gate structure | Wen-Hsing Hsieh | 2017-07-04 |
| 9691695 | Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure | Ta-Pen Guo, Carlos H. Diaz, Yi-Hsiung Lin | 2017-06-27 |
| 9680012 | Semiconductor device structure and method for forming the same | Carlos H. Diaz, Jonathan Tsung-Yung Chang, Yue-Der Chih | 2017-06-13 |
| 9673209 | Memory device and method for fabricating the same | Ta-Pen Guo, Carlos H. Diaz | 2017-06-06 |
| 9660107 | 3D cross-bar nonvolatile memory | Carlos H. Diaz, Ta-Pen Guo | 2017-05-23 |
| 9659632 | SRAM with stacked bit cells | Ta-Pen Guo, Carlos H. Diaz, Chih-Hao Wang | 2017-05-23 |
| 9653604 | Semiconductor device and manufacturing method thereof | Carlos H. Diaz | 2017-05-16 |
| 9653457 | Stacked device and associated layout structure | Ta-Pen Guo, Carlos H. Diaz, Chih-Hao Wang | 2017-05-16 |
| 9647117 | Apparatus and method for forming semiconductor contacts | — | 2017-05-09 |
| 9640645 | Semiconductor device with silicide | Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz | 2017-05-02 |
| 9634091 | Silicon and silicon germanium nanowire formation | Kuo-Cheng Ching, Carlos H. Diaz | 2017-04-25 |
| 9634132 | Semiconductor structures and methods for multi-level band gap energy of nanowire transistors to improve drive current | Tsung-Hsing Yu, Chia-Wen Liu, Yeh Hsu | 2017-04-25 |
| 9620591 | Semiconductor structures and methods for multi-level work function and multi-valued channel doping of nanowire transistors to improve drive current | Tsung-Hsing Yu, Yeh Hsu, Chia-Wen Liu | 2017-04-11 |
| 9620422 | Semiconductor arrangement | Chung-Cheng Wu, Sang Hoo Dhong, Ta-Pen Guo | 2017-04-11 |
| 9614059 | Forming conductive STI liners for FinFETs | — | 2017-04-04 |
| 9614091 | Gate structure and method for fabricating the same | Ta-Pen Guo, Carlos H. Diaz | 2017-04-04 |