Issued Patents 2017
Showing 276–300 of 370 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9614087 | Strained vertical field-effect transistor (FET) and method of forming the same | Juntao Li, Peng Xu | 2017-04-04 |
| 9614077 | Vertical finfet with strained channel | Ramachandra Divakaruni, Juntao Li | 2017-04-04 |
| 9614040 | Strained silicon germanium fin with block source/drain epitaxy and improved overlay capacitance | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-04-04 |
| 9614037 | Nano-ribbon channel transistor with back-bias control | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-04-04 |
| 9613954 | Selective removal of semiconductor fins | Veeraraghavan S. Basker, Ali Khakifirooz | 2017-04-04 |
| 9613869 | FinFET devices | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2017-04-04 |
| 9612224 | High density nano-array for sensing | Qing Cao, Zhengwen Li, Fei Liu, Zhen Zhang | 2017-04-04 |
| 9607898 | Simultaneously fabricating a high voltage transistor and a finFET | Ali Khakifirooz, Alexander Reznicek, Charan V. Surisetty | 2017-03-28 |
| 9608068 | Substrate with strained and relaxed silicon regions | Bruce B. Doris, Pouya Hashemi, Hong He, Alexander Reznicek | 2017-03-28 |
| 9608067 | Hybrid aspect ratio trapping | Ramachandra Divakaruni, Hong He, Juntao Li | 2017-03-28 |
| 9608065 | Air gap spacer for metal gates | Marc A. Bergendahl, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan | 2017-03-28 |
| 9607990 | Method to form strained nFET and strained pFET nanowires on a same substrate | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2017-03-28 |
| 9607943 | Capacitors | Veeraraghavan S. Basker, Christopher J. Penny, Theodorus E. Standaert, Junli Wang | 2017-03-28 |
| 9607899 | Integration of vertical transistors with 3D long channel transistors | Xin Miao, Wenyu Xu, Chen Zhang | 2017-03-28 |
| 9601347 | Forming semiconductor fins with self-aligned patterning | Fee Li Lie, Peng Xu | 2017-03-21 |
| 9601514 | Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy | Juntao Li | 2017-03-21 |
| 9601511 | Low leakage dual STI integrated circuit including FDSOI transistors | Maud Vinet, Bruce B. Doris, Laurent Grenouillet, Ali Khakifirooz, Yannick Le Tiec +1 more | 2017-03-21 |
| 9601378 | Semiconductor fins for FinFET devices and sidewall image transfer (SIT) processes for manufacturing the same | Veeraraghavan S. Basker, Theodorus E. Standaert | 2017-03-21 |
| 9601345 | Fin trimming in a double sit process | Matthew E. Colburn, Bruce B. Doris, Ali Khakifirooz | 2017-03-21 |
| 9595578 | Undercut insulating regions for silicon-on-insulator device | Bruce B. Doris, Balasubramanian Pranatharthiharan, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita | 2017-03-14 |
| 9595613 | Forming semiconductor fins with self-aligned patterning | Fee Li Lie, Peng Xu | 2017-03-14 |
| 9595605 | Vertical single electron transistor formed by condensation | Xin Miao, Wenyu Xu, Chen Zhang | 2017-03-14 |
| 9595595 | Method of forming field effect transistors (FETs) with abrupt junctions and integrated circuit chips with the FETs | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2017-03-14 |
| 9595525 | Semiconductor device including nanowire transistors with hybrid channels | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2017-03-14 |
| 9589833 | Preventing leakage inside air-gap spacer during contact formation | Ruilong Xie, Tenko Yamashita | 2017-03-07 |