Issued Patents 2017
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9768055 | Isolation regions for SOI devices | Qing Liu, Nicolas Loubet, Prasanna Khare, Shom Ponoth, Bruce B. Doris | 2017-09-19 |
| 9721850 | Method for making a three dimensional integrated electronic circuit | Bernard Previtali | 2017-08-01 |
| 9711567 | Process for fabricating an integrated circuit cointegrating a FET transistor and an OxRAM memory location | Laurent Grenouillet, Yves Morand | 2017-07-18 |
| 9673329 | Method for manufacturing a fin MOS transistor | Yves Morand, Romain Wacquez, Laurent Grenouillet, Yannick Le Tiec | 2017-06-06 |
| 9634103 | CMOS in situ doped flow with independently tunable spacer thickness | Laurent Grenouillet, Qing Liu | 2017-04-25 |
| 9601511 | Low leakage dual STI integrated circuit including FDSOI transistors | Kangguo Cheng, Bruce B. Doris, Laurent Grenouillet, Ali Khakifirooz, Yannick Le Tiec +1 more | 2017-03-21 |
| 9570340 | Method of etching a crystalline semiconductor material by ion implantation and then chemical etching based on hydrogen chloride | Laurent Grenouillet, Romain Wacquez | 2017-02-14 |
| 9570465 | Dual STI integrated circuit including FDSOI transistors and method for manufacturing the same | Kangguo Cheng, Bruce B. Doris, Laurent Grenouillet, Ali Khakifirooz, Yannick Le Tiec +1 more | 2017-02-14 |