Issued Patents 2017
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9853130 | Method of modifying the strain state of a semiconducting structure with stacked transistor channels | Sylvain Maitrejean, Emmanuel Augendre, Jean-Charles Barbe, Benoit Mathieu | 2017-12-26 |
| 9831319 | Transistor with MIS connections and fabricating process | Julien BORREL, Louis HUTIN, Fabrice Nemouchi, Heimanu Niebojewski | 2017-11-28 |
| 9711567 | Process for fabricating an integrated circuit cointegrating a FET transistor and an OxRAM memory location | Laurent Grenouillet, Maud Vinet | 2017-07-18 |
| 9673329 | Method for manufacturing a fin MOS transistor | Romain Wacquez, Laurent Grenouillet, Yannick Le Tiec, Maud Vinet | 2017-06-06 |
| 9536951 | FinFET transistor comprising portions of SiGe with a crystal orientation [111] | Sylvain Maitrejean, Emmanuel Augendre, Louis HUTIN | 2017-01-03 |