Issued Patents 2016
Showing 26–50 of 83 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9472616 | Undercut insulating regions for silicon-on-insulator device | Kangguo Cheng, Bruce B. Doris, Balasubramanian Pranatharthiharan, Shom Ponoth, Theodorus E. Standaert | 2016-10-18 |
| 9466570 | MOSFET with asymmetric self-aligned contact | Kangguo Cheng, Xin Miao, Ruilong Xie | 2016-10-11 |
| 9455317 | Nanowire semiconductor device including lateral-etch barrier region | Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh | 2016-09-27 |
| 9455331 | Method and structure of forming controllable unmerged epitaxial material | Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Ruilong Xie | 2016-09-27 |
| 9443775 | Lithography process monitoring of local interconnect continuity | Hyun-Jin Cho, Chun-Chen Yeh, Hui Zang | 2016-09-13 |
| 9437445 | Dual fin integration for electron and hole mobility enhancement | Chia-Yu Chen, Zuoguang Liu, Miaomiao Wang | 2016-09-06 |
| 9437501 | Stacked nanowire device width adjustment by gas cluster ion beam (GCIB) | Kangguo Cheng, Xin Miao, Ruilong Xie | 2016-09-06 |
| 9437499 | Semiconductor device including merged-unmerged work function metal and variable fin pitch | Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh | 2016-09-06 |
| 9431265 | Fin cut for tight fin pitch by two different sit hard mask materials on fin | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2016-08-30 |
| 9425105 | Semiconductor device including self-aligned gate structure and improved gate spacer topography | Veeraraghavan S. Basker | 2016-08-23 |
| 9425292 | Field effect transistor device spacers | Xiuyu Cai, Sanjay C. Mehta | 2016-08-23 |
| 9425184 | Electrostatic discharge devices and methods of manufacture | Huiming Bu, Junjun Li, Theodorus E. Standaert | 2016-08-23 |
| 9418902 | Forming isolated fins from a substrate | Kangguo Cheng, Shom Ponoth, Balasubramanian Pranatharthiharan, Theodorus E. Standaert | 2016-08-16 |
| 9412641 | FinFET having controlled dielectric region height | Dechao Guo, Zuoguang Liu, Chun-Chen Yeh | 2016-08-09 |
| 9412596 | Nitridation on HDP oxide before high-k deposition to prevent oxygen ingress | Takashi Ando, Veeraraghavan S. Basker, Johnathan E. Faltermeier, Hemanth Jagannathan | 2016-08-09 |
| 9412643 | Shallow trench isolation for end fin variation control | Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh | 2016-08-09 |
| 9412820 | Semiconductor device with thinned channel region and related methods | Qing Liu, Chun-Chen Yeh, Veeraraghavan S. Basker | 2016-08-09 |
| 9412840 | Sacrificial layer for replacement metal semiconductor alloy contact formation | Effendi Leobandung | 2016-08-09 |
| 9406548 | Formation of isolation surrounding well implantation | Kangguo Cheng, Shom Ponoth, Theodorus E. Standaert | 2016-08-02 |
| 9406665 | Integrated passive devices for finFET technologies | Thomas N. Adam, Kangguo Cheng, Balasubramanian Pranatharthi Haran, Shom Ponoth, Theodorus E. Standaert | 2016-08-02 |
| 9406570 | FinFET device | Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus E. Standaert | 2016-08-02 |
| 9391152 | Implantation formed metal-insulator-semiconductor (MIS) contacts | Chia-Yu Chen, Zuoguang Liu, Chun-Chen Yeh | 2016-07-12 |
| 9391074 | Structure for FinFET fins | Effendi Leobandung | 2016-07-12 |
| 9390981 | Method of forming a complementary metal oxide semiconductor structure with N-type and P-type field effect transistors having symmetric source/drain junctions and optional dual silicides | Veeraraghavan S. Basker, Andres Bryant | 2016-07-12 |
| 9385050 | Structure and method to fabricate resistor on finFET processes | Wilfried E. Haensch, Pranita Kulkarni | 2016-07-05 |