SP

Sampath Purushothaman

IBM: 11 patents #49 of 5,539Top 1%
📍 Yorktown Heights, NY: #2 of 139 inventorsTop 2%
🗺 New York: #57 of 9,423 inventorsTop 1%
Overall (2003): #1,207 of 273,478Top 1%
11
Patents 2003

Issued Patents 2003

Showing 1–11 of 11 patents

Patent #TitleCo-InventorsDate
6661098 High density area array solder microjoining interconnect structure and fabrication method John Harold Magerlein, Kevin S. Petrarca, Carlos J. Sambucetti, Richard P. Volant, George F. Walker 2003-12-09
6657305 Semiconductor recessed mask interconnect technology Stephen A. Cohen, Timothy J. Dalton, John A. Fitzsimmons, Stephen M. Gates, Brian Herbst +1 more 2003-12-02
6646355 Structure comprising beam leads bonded with electrically conductive adhesive Sung Kwon Kang 2003-11-11
6641899 Nonlithographic method to produce masks by selective reaction, articles produced, and composition for same Matthew E. Colburn, Stephen M. Gates, Jeffrey Hedrick, Elbert E. Huang, Satyanarayana V. Nitta +1 more 2003-11-04
6632314 Method of making a lamination and surface planarization for multilayer thin film interconnect RongQing Yu, Kimberley A. Kelly, Chandrika Prasad, Sung Kwon Kang 2003-10-14
6603204 Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics Stephen M. Gates, Jeffrey Hedrick, Satyanarayana V. Nitta, Cristy Sensenich Tyberg 2003-08-05
6583847 Self alignment of substrates by magnetic alignment Alessandro C. Callegari, Praveen Chaudhari, James P. Doyle, Eileen A. Galligan, James A. Lacey +3 more 2003-06-24
6577011 Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same Leena Paivikki Buchwalter, Alessandro C. Callegari, Stephan A. Cohen, Teresita O. Graham, John P. Hummel +3 more 2003-06-10
6569707 Method for improving performance of organic semiconductors in bottom electrode structure Christos D. Dimitrakopoulos, Ioannis Kymissis 2003-05-27
6555762 Electronic package having substrate with electrically conductive through holes filled with polymer and conductive composition Bernd Karl Appelt, Jeffrey D. Gelorme, Sung Kwon Kang, Voya R. Markovich, Kostas Papathomas 2003-04-29
6537908 Method for dual-damascence patterning of low-k interconnects using spin-on distributed hardmask Ann R. Fornof, Stephen M. Gates, Jeffrey Hedrick, Satyanarayana V. Nitta, Christy S. Tyberg 2003-03-25