Issued Patents All Time
Showing 26–50 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10260150 | Method and system for sculpting spacer sidewall mask | Vinh Luong | 2019-04-16 |
| 10217670 | Wrap-around contact integration scheme | Kandabara Tapily, Satoru Nakamura, Soo Doo Chae, Kaoru Maekawa, Gerrit J. Leusink | 2019-02-26 |
| 10170329 | Spacer formation for self-aligned multi-patterning technique | Eric Chih-Fang Liu | 2019-01-01 |
| 10049875 | Trim method for patterning during various stages of an integration scheme | Angelique Raley | 2018-08-14 |
| 9978563 | Plasma treatment method to meet line edge roughness and other integration objectives | Vinh Luong | 2018-05-22 |
| 9899219 | Trimming inorganic resists with selected etchant gas mixture and modulation of operating variables | Vinh Luong | 2018-02-20 |
| 9812325 | Method for modifying spacer profile | Nihar Mohanty | 2017-11-07 |
| 9786503 | Method for increasing pattern density in self-aligned patterning schemes without using hard masks | Angelique Raley, Nihar Mohanty | 2017-10-10 |
| 9697990 | Etching method for a structure pattern layer having a first material and second material | Satoru Nakamura | 2017-07-04 |
| 9673059 | Method for increasing pattern density in self-aligned patterning integration schemes | Angelique Raley | 2017-06-06 |
| 9576812 | Partial etch memorization via flash addition | Elliott Franke, Vinayak Rastogi, Kiyohito Ito | 2017-02-21 |
| 9570313 | Method for etching high-K dielectric using pulsed bias power | Alok Ranjan | 2017-02-14 |
| 9520270 | Direct current superposition curing for resist reflow temperature enhancement | Nihar Mohanty, Chi-Chun Liu | 2016-12-13 |
| 9443731 | Material processing to achieve sub-10nm patterning | David L. O'Meara, Angelique Raley, Kiyohito Ito | 2016-09-13 |
| 9257280 | Mitigation of asymmetrical profile in self aligned patterning etch | Angelique Raley, Kiyohito Ito | 2016-02-09 |
| 9165765 | Method for patterning differing critical dimensions at sub-resolution scales | Angelique Raley | 2015-10-20 |
| 9159575 | Method for etching high-K dielectric using pulsed bias power | Alok Ranjan | 2015-10-13 |
| 9153457 | Etch process for reducing directed self assembly pattern defectivity using direct current positioning | Vidhya Chakrapani, Kaushik A. Kumar | 2015-10-06 |
| 8980111 | Sidewall image transfer method for low aspect ratio patterns | Kosuke Ogasawara | 2015-03-17 |
| 8945408 | Etch process for reducing directed self assembly pattern defectivity | Vidhya Chakrapani, Kaushik A. Kumar | 2015-02-03 |
| 8735291 | Method for etching high-k dielectric using pulsed bias power | Alok Ranjan | 2014-05-27 |
| 8501628 | Differential metal gate etching process | Vinh Luong, Hiroyuki Takahashi, Asao Yamashita, Vaidya Bharadwaj, Takashi Enomoto +1 more | 2013-08-06 |
| 8334083 | Etch process for controlling pattern CD and integrity in multi-layer masks | Vinh Luong | 2012-12-18 |
| 8313661 | Deep trench liner removal process | Vinh Luong | 2012-11-20 |
| 8282844 | Method for etching metal nitride with high selectivity to other materials | Hiroyuki Takahashi, Masayuki Sawataishi | 2012-10-09 |