Issued Patents All Time
Showing 26–50 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10763230 | Integrated circuit backside metallization | Hiroyuki Sada, Shoichi Iriguchi, Genki Yano, Luu Thanh Nguyen, Ashok S. Prabhu +2 more | 2020-09-01 |
| 10763231 | Bump bond structure for enhanced electromigration performance | Dibyajat Mishra, Ashok S. Prabhu, Tomoko Noguchi, Luu Thanh Nguyen, Makoto Yoshino +1 more | 2020-09-01 |
| 10748827 | Packaged semiconductor devices for high voltage with die edge protection | Woochan Kim, Vivek Kishorechand Arora | 2020-08-18 |
| 10734313 | Integration of a passive component in an integrated circuit package | Jeffrey Anthony Morroni, Rajeev Joshi, Sreenivasan K. Koduri, Sujan Kundapur Manohar, Yogesh Kumar Ramadass | 2020-08-04 |
| 10650957 | Additive deposition low temperature curable magnetic interconnecting layer for power components integration | Yi Yan, Luu Thanh Nguyen, Ashok S. Prabhu | 2020-05-12 |
| 10580715 | Stress buffer layer in embedded package | Woochan Kim, Masamitsu Matsuura, Mutsumi Masumoto, Kengo Aoya, Hau Nguyen +1 more | 2020-03-03 |
| 10580722 | High voltage flip-chip on lead (FOL) package | Thomas D. Bonifield, Woochan Kim, Vivek Kishorechand Arora | 2020-03-03 |
| 10573582 | Semiconductor systems having dual leadframes | Rajeev Joshi, Hau Nguyen, Ken Pham | 2020-02-25 |
| 10541220 | Printed repassivation for wafer chip scale packaging | Daiki Komatsu, Makoto Shibuya, Yi Yan, Hau Nguyen, Luu Thanh Nguyen | 2020-01-21 |
| 10312184 | Semiconductor systems having premolded dual leadframes | Rajeev Joshi, Hau Nguyen, Ken Pham | 2019-06-04 |
| 9663357 | Open cavity package using chip-embedding technology | Jie Mao, Hau Nguyen, Luu Thanh Nguyen | 2017-05-30 |
| 9035422 | Multilayer high voltage isolation barrier in an integrated circuit | Vijaylaxmi Khanolkar, Randall L. Walberg, Giovanni Frattini, Roberto Giampiero Massolini | 2015-05-19 |
| 8716830 | Thermally efficient integrated circuit package | Luu Thanh Nguyen | 2014-05-06 |
| 8674418 | Method and apparatus for achieving galvanic isolation in package having integral isolation medium | Vijaylaxmi Khanolkar, Ashok S. Prabhu, Peter Johnson | 2014-03-18 |
| 8450151 | Micro surface mount device packaging | Tao Feng, Will K. Wong | 2013-05-28 |
| 8283760 | Lead frame interconnect scheme with high power density | Ken Pham, Ashok S. Prabhu | 2012-10-09 |
| 8101470 | Foil based semiconductor package | Nghia Thuc Tu, Jaime A. Bayan, Will K. Wong, David Chin | 2012-01-24 |
| 7923825 | Integrated circuit package | Jaime A. Bayan | 2011-04-12 |
| 7838974 | Intergrated circuit packaging with improved die bonding | Lianxi Shen | 2010-11-23 |
| 7824963 | Inkjet printed leadframe | Randall L. Walberg, Luu Thanh Nguyen | 2010-11-02 |
| 7703993 | Wafer level optoelectronic package with fiber side insertion | Artur Darbinyan, Luu Thanh Nguyen | 2010-04-27 |
| 7705476 | Integrated circuit package | Jaime A. Bayan | 2010-04-27 |
| 7667304 | Inkjet printed leadframes | Randall L. Walberg, Luu Thanh Nguyen | 2010-02-23 |
| 7652379 | Bond pad stacks for ESD under pad and active under pad bonding | — | 2010-01-26 |
| 7615407 | Methods and systems for packaging integrated circuits with integrated passive components | Ashok S. Prabhu | 2009-11-10 |