Issued Patents All Time
Showing 76–100 of 260 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11264088 | Semiconductor memory with respective power voltages for memory cells | Wei-Cheng Wu, Chih-Yu Lin, Kao-Cheng Lin, Wei Min Chan | 2022-03-01 |
| 11264070 | Systems and methods for memory operation using local word lines | Yi-Hsin Nien, Hidehiro Fujiwara | 2022-03-01 |
| 11263331 | Electronic device for checking randomness of identification key device, random key checker circuit, and method of checking randomness of electronic device | Chien-Chen Lin, Hidehiro Fujiwara, Wei Min Chan, Shih-Lien Linus Lu | 2022-03-01 |
| 11238905 | Sense amplifier layout for FinFET technology | Chien-Chi TIEN, Kao-Cheng Lin, Jung-Hsuan Chen | 2022-02-01 |
| 11205475 | Static random access memory with a supplementary driver circuit and method of controlling the same | Chih-Yu Lin, Wei-Cheng Wu, Kao-Cheng Lin | 2021-12-21 |
| 11200946 | Low voltage bit-cell | Mahmut Sinangil, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Ting Lin | 2021-12-14 |
| 11199866 | Voltage regulator with power rail tracking | Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu +2 more | 2021-12-14 |
| 11183234 | Bitcell supporting bit-write-mask function | Hidehiro Fujiwara, Yi-Hsin Nien | 2021-11-23 |
| 11176997 | Memory cell | Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Chien-Chen Lin | 2021-11-16 |
| 11152057 | SRAM memory | Hidehiro Fujiwara, Cheng Chun Dai, Chih-Yu Lin, Hiroki Noguchi | 2021-10-19 |
| 11152301 | Memory cell having multi-level word line | Hidehiro Fujiwara, Li-Wen Wang, Hung-Jen Liao | 2021-10-19 |
| 11145655 | Memory device with reduced-resistance interconnect | Sahil Preet Singh | 2021-10-12 |
| 11100964 | Multi-stage bit line pre-charge | Wei-Cheng Wu, Kao-Cheng Lin, Chih-Cheng Yu, Pei-Yuan Li, Chien-Chen Lin +1 more | 2021-08-24 |
| 11088151 | 4Cpp SRAM cell and array | Hidehiro Fujiwara, Chia-En Huang, Yih Wang | 2021-08-10 |
| 11074966 | Method and system to balance ground bounce | Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Wei Zhao | 2021-07-27 |
| 11062739 | Semiconductor chip having memory and logic cells | Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Wei Zhao | 2021-07-13 |
| 11048840 | Method for eliminating false paths of a circuit unit to be implemented using a system | Chun-Jiun Dai, Hung-Jen Liao, Wei Min Chan | 2021-06-29 |
| 11043264 | Static random access memory method | Wei-Cheng Wu, Wei Min Chan, Hung-Jen Liao, Ping-Wei Wang | 2021-06-22 |
| 11037934 | SRAM circuits with aligned gate electrodes | Fang Chen, Jhon Jhy Liaw, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu | 2021-06-15 |
| 11037644 | Testing circuit, testing method, and apparatus for testing multi-port random access memory | Hidehiro Fujiwara | 2021-06-15 |
| 11031055 | Memory macro and method of operating the same | Chien-Kuo Su, Cheng Hung Lee, Chiting Cheng, Hung-Jen Liao, Jonathan Tsung-Yung Chang +2 more | 2021-06-08 |
| 11024633 | SRAM cell word line structure with reduced RC effects | Hidehiro Fujiwara, Wei Min Chan, Chih-Yu Lin, Hung-Jen Liao | 2021-06-01 |
| 11018142 | Memory cell and method of manufacturing the same | Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yasutoshi Okuno | 2021-05-25 |
| 11011238 | Floating data line circuits and methods | Manish Arora, Hung-Jen Liao, Nikhil Puri, Yu-Hao Hsu | 2021-05-18 |
| 10991423 | Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) | Sahil Preet Singh, Jung-Hsuan Chen, Avinash Chander, Albert Ying | 2021-04-27 |