Issued Patents All Time
Showing 101–125 of 260 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10991420 | Semiconductor device including distributed write driving arrangement and method of operating same | Hidehiro Fujiwara, Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang | 2021-04-27 |
| 10978144 | Integrated circuit and operating method thereof | Chia-En Huang, Hidehiro Fujiwara, Jui-Che Tsai, Yih Wang | 2021-04-13 |
| 10971220 | Write assist for a memory device and methods of forming the same | Sahil Preet Singh, Hung-Jen Liao | 2021-04-06 |
| 10971217 | SRAM cell for interleaved wordline scheme | Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Mahmut Sinangil | 2021-04-06 |
| 10964683 | Memory array circuit and method of manufacturing the same | Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Sahil Preet Singh | 2021-03-30 |
| 10964389 | Memory cell | Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Chien-Chen Lin | 2021-03-30 |
| 10964355 | Memory device with strap cells | Jonathan Tsung-Yung Chang, Cheng Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon Jhy Liaw | 2021-03-30 |
| 10949100 | Configurable memory storage system | Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu +6 more | 2021-03-16 |
| 10943667 | Memory device | Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Hiroki Noguchi, Wei Zhao | 2021-03-09 |
| 10892008 | Multi word line assertion | Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Wei Zhao | 2021-01-12 |
| 10885973 | Memory device and method of controlling memory device | Hidehiro Fujiwara | 2021-01-05 |
| 10878894 | Memory device having low bitline voltage swing in read port and method for reading memory cell | Hidehiro Fujiwara, Haruki Mori, Chih-Yu Lin | 2020-12-29 |
| 10872644 | Boost bypass circuitry in a memory storage device | Hidehiro Fujiwara | 2020-12-22 |
| 10854282 | Memory read stability enhancement with short segmented bit line architecture | Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Sahil Preet Singh | 2020-12-01 |
| 10847214 | Low voltage bit-cell | Mahmut Sinangil, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Ting Lin | 2020-11-24 |
| 10839894 | Memory computation circuit and method | Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2020-11-17 |
| 10832765 | Variation tolerant read assist circuit for SRAM | Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Sahil Preet Singh | 2020-11-10 |
| 10803928 | Low voltage memory device | Mahmut Sinangil, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2020-10-13 |
| 10790015 | Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) | Sahil Preet Singh, Jung-Hsuan Chen, Avinash Chander, Albert Ying | 2020-09-29 |
| 10783955 | Memory circuit having shared word line | Hidehiro Fujiwara, Li-Wen Wang, Hung-Jen Liao | 2020-09-22 |
| 10783954 | Semiconductor memory with respective power voltages for memory cells | Wei-Cheng Wu, Chih-Yu Lin, Kao-Cheng Lin, Wei Min Chan | 2020-09-22 |
| 10770134 | SRAM based authentication circuit | Chien-Chen Lin, Wei Min Chan, Chih-Yu Lin, Shih-Lien Linus Lu | 2020-09-08 |
| 10770131 | SRAM cell for interleaved wordline scheme | Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Mahmut Sinangil | 2020-09-08 |
| 10755768 | Semiconductor device including distributed write driving arrangement and method of operating same | Hidehiro Fujiwara, Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang | 2020-08-25 |
| 10734066 | Static random access memory with write assist circuit | Hidehiro Fujiwara, Chih-Yu Lin, Sahil Preet Singh, Hsien-Yu Pan, Hung-Jen Liao | 2020-08-04 |