Issued Patents All Time
Showing 51–75 of 260 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11657870 | Method and system to balance ground bounce | Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Wei Zhao | 2023-05-23 |
| 11651804 | Memory macro and method of operating the same | Chien-Kuo Su, Chiting Cheng, Pankaj Aggarwal, Cheng Hung Lee, Hung-Jen Liao +2 more | 2023-05-16 |
| 11637108 | Memory array circuit and method of manufacturing same | Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Yasutoshi Okuno, Hung-Jen Liao | 2023-04-25 |
| 11631456 | Bitcell supporting bit-write-mask function | Hidehiro Fujiwara, Yi-Hsin Nien | 2023-04-18 |
| 11610628 | Static random access memory | Wei-Cheng Wu, Hung-Jen Liao, Ping-Wei Wang, Wei Min Chan | 2023-03-21 |
| 11605637 | SRAM circuits with aligned gate electrodes | Fang Chen, Jhon Jhy Liaw, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu | 2023-03-14 |
| 11579648 | Voltage regulator with power rail tracking | Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu +2 more | 2023-02-14 |
| 11574674 | SRAM based authentication circuit | Chien-Chen Lin, Wei Min Chan, Chih-Yu Lin, Shih-Lien Linus Lu | 2023-02-07 |
| 11574098 | Method for eliminating false paths of a circuit unit to be implemented using a system | Chun-Jiun Dai, Hung-Jen Liao, Wei Min Chan | 2023-02-07 |
| 11569246 | Four CPP wide memory cell with buried power grid, and method of fabricating same | Hidehiro Fujiwara, Chih-Yu Lin, Wei Zhao, Yi-Hsin Nien | 2023-01-31 |
| 11562786 | Memory device having a negative voltage circuit | Yi-Hsin Nien, Hidehiro Fujiwara, Chih-Yu Lin | 2023-01-24 |
| 11562946 | Memory macro including through-silicon via | Hidehiro Fujiwara, Tze-Chiang Huang, Hong-Chen Cheng, Hung-Jen Liao, Jonathan Tsung-Yung Chang +2 more | 2023-01-24 |
| 11532351 | Memory device with additional write bit lines | Hidehiro Fujiwara, Chia-En Huang, Jui-Che Tsai, Yih Wang | 2022-12-20 |
| 11514952 | Memory device with strap cells | Jonathan Tsung-Yung Chang, Cheng Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon Jhy Liaw | 2022-11-29 |
| 11423978 | Write assist for a memory device and methods of forming the same | Sahil Preet Singh, Hung-Jen Liao | 2022-08-23 |
| 11423977 | Static random access memory with write assist circuit | Hidehiro Fujiwara, Chih-Yu Lin, Sahil Preet Singh, Hsien-Yu Pan, Hung-Jen Liao | 2022-08-23 |
| 11423974 | Method of forming semiconductor device including distributed write driving arrangement | Hidehiro Fujiwara, Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang | 2022-08-23 |
| 11404115 | Memory with write assist scheme | Hidehiro Fujiwara, Hung-Jen Liao | 2022-08-02 |
| 11404114 | Low voltage memory device | Mahmut Sinangil, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2022-08-02 |
| 11404113 | Memory device including a word line with portions with different sizes in different metal layers | Yi-Hsin Nien, Wei Zhao, Chih-Yu Lin, Hidehiro Fujiwara, Ru-Yu WANG | 2022-08-02 |
| 11398275 | Memory computation circuit and method | Hung-Jen Liao, Jonathan Tsung-Yung Chang, Hidehiro Fujiwara | 2022-07-26 |
| 11398257 | Header layout design including backside power rail | Haruki Mori, Chien-Chi TIEN, Chia-En Huang, Hidehiro Fujiwara, Feng-Lun CHEN | 2022-07-26 |
| 11322198 | Multi word line assertion | Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Wei Zhao | 2022-05-03 |
| 11308999 | Boost bypass circuitry in a memory storage device | Hidehiro Fujiwara | 2022-04-19 |
| 11301148 | Configurable memory storage system | Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu +6 more | 2022-04-12 |