Issued Patents All Time
Showing 26–50 of 260 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12080341 | Memory device including dual control circuits | Hidehiro Fujiwara | 2024-09-03 |
| 12074156 | Memory array circuit and method of manufacturing same | Hidehiro Fujiwara, Sahil Preet Singh, Chih-Yu Lin, Hsien-Yu Pan, Hung-Jen Liao | 2024-08-27 |
| 12041761 | SRAM circuits with aligned gate electrodes | Fang Chen, Jhon Jhy Liaw, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu | 2024-07-16 |
| 12029023 | Memory array circuit and method of manufacturing same | Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Yasutoshi Okuno, Hung-Jen Liao | 2024-07-02 |
| 11997843 | 4CPP SRAM cell and array | Hidehiro Fujiwara, Chia-En Huang, Yih Wang | 2024-05-28 |
| 11989046 | Voltage regulator with power rail tracking | Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu +2 more | 2024-05-21 |
| 11963348 | Integrated circuit read only memory (ROM) structure | Geng-Cing Lin, Ze-Sian Lu, Meng-Sheng Chang, Chia-En Huang, Jung-Ping Yang | 2024-04-16 |
| 11961554 | Shared power footer circuit | Hidehiro Fujiwara, Kao-Cheng Lin, Wei Min Chan | 2024-04-16 |
| 11948627 | Static random access memory with write assist circuit | Hidehiro Fujiwara, Chih-Yu Lin, Sahil Preet Singh, Hsien-Yu Pan, Hung-Jen Liao | 2024-04-02 |
| 11929116 | Memory device having a negative voltage circuit | Yi-Hsin Nien, Hidehiro Fujiwara, Chih-Yu Lin | 2024-03-12 |
| 11854943 | Memory macro including through-silicon via | Hidehiro Fujiwara, Tze-Chiang Huang, Hong-Chen Cheng, Hung-Jen Liao, Jonathan Tsung-Yung Chang +2 more | 2023-12-26 |
| 11830544 | Write assist for a memory device and methods of forming the same | Sahil Preet Singh, Hung-Jen Liao | 2023-11-28 |
| 11830543 | Memory computation circuit | Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2023-11-28 |
| 11798632 | Floating data line circuit and method | Manish Arora, Hung-Jen Liao, Nikhil Puri, Yu-Hao Hsu | 2023-10-24 |
| 11783890 | Semiconductor device including distributed write driving arrangement | Hidehiro Fujiwara, Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang | 2023-10-10 |
| 11778802 | SRAM cell word line structure with reduced RC effects | Hidehiro Fujiwara, Wei Min Chan, Chih-Yu Lin, Hung-Jen Liao | 2023-10-03 |
| 11769533 | Semiconductor chip having memory and logic cells | Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Wei Zhao | 2023-09-26 |
| 11763882 | Low voltage memory device | Mahmut Sinangil, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2023-09-19 |
| 11749321 | Multi-stage bit line pre-charge | Wei-Cheng Wu, Kao-Cheng Lin, Chih-Cheng Yu, Pei-Yuan Li, Chien-Chen Lin +1 more | 2023-09-05 |
| 11723194 | Integrated circuit read only memory (ROM) structure | Geng-Cing Lin, Ze-Sian Lu, Meng-Sheng Chang, Chia-En Huang, Jung-Ping Yang | 2023-08-08 |
| 11715501 | Header layout design including backside power rail | Haruki Mori, Chien-Chi TIEN, Chia-En Huang, Hidehiro Fujiwara, Feng-Lun CHEN | 2023-08-01 |
| 11714570 | Computing-in-memory device and method | Jonathan Tsung-Yung Chang, Hidehiro Fujiwara, Hung-Jen Liao, Yih Wang, Haruki Mori | 2023-08-01 |
| 11682440 | Systems and methods for memory operation using local word lines | Yi-Hsin Nien, Hidehiro Fujiwara | 2023-06-20 |
| 11676660 | Static random access memory with a supplementary driver circuit and method of controlling the same | Chih-Yu Lin, Wei-Cheng Wu, Kao-Cheng Lin | 2023-06-13 |
| 11675505 | Configurable memory storage system | Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu +6 more | 2023-06-13 |